PMN49EN
N-channel TrenchMOS logic level FET
Rev. 01 — 13 April 2007
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology.
1.2 Features
I
Logic level threshold
I
Fast switching
1.3 Applications
I
Battery management
I
High-speed switching
1.4 Quick reference data
I
V
DS
≤
30 V
I
R
DSon
≤
47 mΩ
I
I
D
≤
4.6 A
I
Q
GD
= 1.6 nC (typ)
2. Pinning information
Table 1.
Pin
1, 2, 5, 6
3
4
Pinning
Description
drain (D)
gate (G)
source (S)
1
2
3
mbb076
Simplified outline
6
5
4
Symbol
D
G
S
SOT457 (TSOP6)
NXP Semiconductors
PMN49EN
N-channel TrenchMOS logic level FET
3. Ordering information
Table 2.
Ordering information
Package
Name
PMN49EN
SC-74
Description
plastic surface-mounted package (TSOP6); 6 leads
Version
SOT457
Type number
4. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
V
DS
V
DGR
V
GS
I
D
I
DM
P
tot
T
stg
T
j
I
S
I
SM
drain-source voltage
drain-gate voltage (DC)
gate-source voltage
drain current
peak drain current
total power dissipation
storage temperature
junction temperature
source current
peak source current
T
sp
= 25
°C
T
sp
= 25
°C;
pulsed; t
p
≤
10
µs
T
sp
= 25
°C;
V
GS
= 10 V; see
Figure 2
and
3
T
sp
= 100
°C;
V
GS
= 10 V; see
Figure 2
T
sp
= 25
°C;
pulsed; t
p
≤
10
µs;
see
Figure 3
T
sp
= 25
°C;
see
Figure 1
Conditions
25
°C ≤
T
j
≤
150
°C
25
°C ≤
T
j
≤
150
°C;
R
GS
= 20 kΩ
Min
-
-
-
-
-
-
-
−55
−55
-
-
Max
30
30
±20
4.6
2.9
18.4
1.75
+150
+150
1.4
5.6
Unit
V
V
V
A
A
A
W
°C
°C
A
A
Source-drain diode
PMN49EN_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 13 April 2007
2 of 12
NXP Semiconductors
PMN49EN
N-channel TrenchMOS logic level FET
120
P
der
(%)
80
03aa17
120
I
der
(%)
80
03aa25
40
40
0
0
50
100
150
T
sp
(
°
C)
200
0
0
50
100
150
T
sp
(
°
C)
200
P
tot
P
der
=
-----------------------
×
100
%
-
P
tot
(
25°C
)
Fig 1. Normalized total power dissipation as a
function of solder point temperature
10
2
I
D
(A)
10
Limit R
DSon
= V
DS
/ I
D
I
D
I
der
=
-------------------
×
100
%
-
I
D
(
25°C
)
Fig 2. Normalized continuous drain current as a
function of solder point temperature
003aab227
t
p
= 10
µ
s
100
µ
s
1
DC
10
-1
1 ms
10 ms
100 ms
10
-2
10
-1
1
10
V
DS
(V)
10
2
T
sp
= 25
°C;
I
DM
is single pulse
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PMN49EN_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 13 April 2007
3 of 12
NXP Semiconductors
PMN49EN
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 4.
R
th(j-sp)
Thermal characteristics
Conditions
see
Figure 4
Min
-
Typ
-
Max
70
Unit
K/W
thermal resistance from junction to solder point
Symbol Parameter
10
2
Z
th(j-sp)
(K/W)
10
δ =
0.5
0.2
0.1
0.05
0.02
1
single pulse
P
003aab596
δ
=
t
p
T
t
p
t
T
10
-1
10
-5
10
-4
10
-3
10
-2
10
-1
1
t
p
(s)
10
Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration
PMN49EN_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 13 April 2007
4 of 12
NXP Semiconductors
PMN49EN
N-channel TrenchMOS logic level FET
6. Characteristics
Table 5.
Characteristics
T
j
= 25
°
C unless otherwise specified.
Symbol Parameter
Static characteristics
V
(BR)DSS
drain-source breakdown
voltage
I
D
= 250
µA;
V
GS
= 0 V
T
j
= 25
°C
T
j
=
−55 °C
V
GS(th)
gate-source threshold voltage
I
D
= 1 mA; V
DS
= V
GS
; see
Figure 9
and
10
T
j
= 25
°C
T
j
= 150
°C
T
j
=
−55 °C
I
DSS
drain leakage current
V
DS
= 30 V; V
GS
= 0 V
T
j
= 25
°C
T
j
= 150
°C
I
GSS
R
G
R
DSon
gate leakage current
gate resistance
drain-source on-state
resistance
V
GS
=
±20
V; V
DS
= 0 V
f = 1 MHz; V
GSS(AC)
= 150 mV
V
GS
= 10 V; I
D
= 2 A; see
Figure 6
and
8
T
j
= 25
°C
T
j
= 150
°C
V
GS
= 4.5 V; I
D
= 1.5 A; see
Figure 6
and
8
Dynamic characteristics
Q
G(tot)
Q
GS
Q
GD
V
GS(pl)
C
iss
C
oss
C
rss
C
iss
t
d(on)
t
r
t
d(off)
t
f
V
SD
t
rr
Q
r
total gate charge
gate-source charge
gate-drain charge
gate-source plateau voltage
input capacitance
output capacitance
reverse transfer capacitance
input capacitance
turn-on delay time
rise time
turn-off delay time
fall time
source-drain voltage
reverse recovery time
recovered charge
I
S
= 1.5 A; V
GS
= 0 V; see
Figure 13
I
S
= 2 A; dI
S
/dt =
−100
A/µs; V
GS
= 0 V
V
GS
= 0 V; V
DS
= 0 V; f = 1 MHz
V
DS
= 15 V; R
L
= 15
Ω;
V
GS
= 10 V; R
G
= 6
Ω
V
GS
= 0 V; V
DS
= 30 V; f = 1 MHz;
see
Figure 14
I
D
= 3 A; V
DS
= 15 V; V
GS
= 4.5 V;
see
Figure 11
and
12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
8.8
1.1
1.6
2.83
350
100
64.1
570
4.1
4.3
12.9
4.9
0.79
0.73
-
-
-
-
-
-
-
-
-
-
-
-
1.2
-
nC
nC
nC
V
pF
pF
pF
pF
ns
ns
ns
ns
V
ns
nC
-
-
-
40
68
49
47
80
60
mΩ
mΩ
mΩ
-
-
-
-
-
-
10
1.9
1
100
100
-
µA
µA
nA
Ω
1
0.6
-
1.5
-
-
2
-
2.2
V
V
V
30
27
-
-
-
-
V
V
Conditions
Min
Typ
Max
Unit
Source-drain diode
19.25 -
PMN49EN_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 13 April 2007
5 of 12
京公网安备 11010802033920号
EEWORLD
