February1997
Revision 1.1
DATA SHEET
ESA8UN324(2/4)-(60/70)(J/T)(G/S)-S
32MByte (8M x 32) CMOS EDO DRAM Module
General Description
The ESA8UN324(2/4)-(60/70()J/T)(G/S)-S is a high performance, EDO (Extended Data Out) 32-megabyte dynamic RAM module
organized as 4M words by 32bits, in a 72-pin, leadless, single-in-line memory module (SIMM) package. ESA8UN3242 supports
2K refresh. ESA8UN3244 supports 4K refresh.
The module utilizes sixteen, Fujitsu MB811(7/6)405A-(60/70)PJ CMOS 4Mx4 EDO dynamic RAM in a surface mount package
on an epoxy laminate substrate. Each device is accompanied by a decoupling capacitor for improved noise immunity.
Control lines provided are such that byte control is possible.
Features
• High Density: 32MByte
• Fast Access Time of 60/70 ns (max.)
• Low Power:
Active (60/70 ns)
4.7/4.0 W (max.) - 2K
3.4/2.9 W (max.) - 4K
176mW (max.) - Standby (TTL)
88mW (max.) - Standby (CMOS)
• TTL-compatible inputs and outputs
• Separate power and ground planes
• Single power supply of 5V±10%
• Height: 1.00 inch
ABSOLUTE MAXIMUM RATINGS
Item
Voltage on any pin relative to V
SS
Power Dissipation
Operating Temperature
Storage Temperate
Short Circuit Output Current
Symbol
V
T
P
T
T
opr
T
stg
I
OS
Ratings
-1 to +7.0
8
0 to +70
-55 to +125
-50 to +50
Unit
V
W
°
C
°
C
mA
RECOMMENDED DC OPERATING CONDITIONS
(T
A
= 0 to +70
°C)
Symbol
V
CC
V
SS
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High voltage
Input Low voltage
Min
4.5
0
2.4
-1
Typ
5.0
0
-
-
Max
5.5
0
V
CC
+1
0.8
Unit
V
V
V
V
Fujitsu Microelectronics, Inc.
1
February 1997
Revision 1.1
ESA8UN324(2/4)-(60/70)(J/T)(G/S)-S
Functional Diagram
CAS3*
CAS2*
CAS1*
CAS0*
4M x 8
Block
4M x 8
Block
4M x 8
Block
4M x 8
Block
RAS0*
RAS2*
RAS1*
4M x 8
Block
DQ0~DQ7
4M x 8
Block
DQ8~DQ15
4M x 8
Block
DQ16~DQ23
4M x 8
Block
DQ24~DQ31
RAS3*
DQ0~DQ31
V
CC
(All specifications of the device are subject to change without notice.)
V
SS
Decoupling capacitors
to all devices
Notes:
1.
2.
3.
4.
A0 ~ A10/A11 to all devices (A11 is NC for 2K refresh module).
WE* to all devices.
OE* of all devices is grounded.
Each 4Mx8 Block consists of two 4Mx4 devices.
2
Fujitsu Microelectronics, Inc.
February 1997
Revision 1.1
ESA8UN324(2/4)-(60/70)(J/T)(G/S)-S
Pin Name
A0~A10†
A0~A11
A0~A9
DQ0~DQ31
CAS0*~CAS3*
RAS0~RAS3
Addresses for 2K Refresh Module
Row Addresses for 4K Refresh Module
Column Addresses for 4K Refresh Module
Data Inputs/Outputs
Column Address Strobes
Row Address Strobes
WE*
PD1~PD4
V
CC
V
SS
NC
Write Enable
Presence Detects
Power Supply
Ground
No Connection
Presence Detect Pins
Pin
PD1
PD2
PD3
PD4
-60
NC
V
SS
NC
NC
-70
NC
V
SS
V
SS
NC
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Pin Designation
V
SS
DQ0
DQ16
DQ1
DQ17
DQ2
DQ18
DQ3
DQ19
V
CC
NC
A0
A1
A2
A3
A4
A5
A6
Pin No.
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Pin Designation
A10
DQ4
DQ20
DQ5
DQ21
DQ6
DQ22
DQ7
DQ23
A7
A11†
V
CC
A8
A9
RAS3*
RAS2*
NC
NC
Pin No.
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
Pin Designation
NC
NC
V
SS
CAS0*
CAS2*
CAS3*
CAS1*
RAS0*
RAS1*
NC
WE*
NC
DQ8
DQ24
DQ9
DQ25
DQ10
DQ26
Pin No.
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Pin Designation
DQ11
DQ27
DQ12
DQ28
V
CC
DQ29
DQ13
DQ30
DQ14
DQ31
DQ15
NC
PD1
PD2
PD3
PD4
NC
V
SS
†: A11 is NC for 2K refresh module.
Fujitsu Microelectronics, Inc.
3
February 1997
Revision 1.1
ESA8UN324(2/4)-(60/70)(J/T)(G/S)-S
DC CHARACTERISTICS
(V
CC
= 5.0V±10%, V
SS
= 0V, T
A
= 0 to +70
°C)
60
Parameter
Symbol
Test Condition
Refresh
Min.
Operating Current
I
CC1
RAS*, CAS* cycling; t
RC
= min.
TTL Interface
RAS*, CAS* = V
IH
D
out
= High-Z
CMOS Interface
RAS*, CAS*
≥
V
cc
- 0.2V
D
out
= High-Z
CAS* = V
IH
; RAS*, Address
cycling @ t
RC
= min
RAS*, CAS* cycling @
t
RC
= min.
RAS* = V
IL
; CAS*, Address
cycling @ t
PC
= min
0V
≤
V
in
≤
V
CC
+0.5V
0V
≤
V
out
≤
V
CC
D
out
= Disable
High I
out
= -5 mA
Low I
out
= 4.5 mA
2K
4K
2K
4K
2K
4K
2K
4K
-
-
-
Max.
856
616
32
Min.
-
-
-
Max.
736
mA
536
32
mA
1, 2
70
Unit
Note
Standby current
I
CC2
-
-
-
-
-
-
-
-160
-20
2.4
-
16
856
616
856
616
856
616
160
20
-
0.4
-
-
-
-
-
-
-
-160
-20
2.4
-
16
720
mA
RAS* -only Refresh
Current
CAS*-before-RAS*
Refresh Current
Fast Page Mode
Current
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
Notes:
1.
2.
3.
I
CC3
mA
536
736
mA
536
736
mA
536
160
20
-
0.4
2
I
CC4
I
CC5
I
LI
I
LO
V
OH
V
OL
1, 3
µ
A
µ
A
V
V
Values depend on load condition when the device is selected. Maximum Values are specified at the output open condition.
Address can be changed once or less while RAS* = V
IL
.
Address can be changed once or less while CAS* = V
IH
.
CAPACITANCE
(TA =+25°C, V
CC
= 5.0V±10%=10V)
Parameter
Input Capacitance (Address)
Input Capacitance (RAS0*~RAS3*)
Input Capacitance (CAS0*~CAS3*)
Input Capacitance (WE*)
Input/Output Capacitance (DQ0~DQ31)
Notes:
1.
2.
Symbol
C
I1
C
I2
C
I3
C
I4
C
I/O
Max.
85
25
25
85
12
Unit
pF
pF
pF
pF
pF
Note
1
1
1
1
1, 2
Capacitance is measured with Boonton Meter or effective capacitance method.
CAS* = V
IH
to disable D
out
.
4
Fujitsu Microelectronics, Inc.
February 1997
Revision 1.1
ESA8UN324(2/4)-(60/70)(J/T)(G/S)-S
AC CHARACTERISTICS
(TA = 0 to +70°C, V
CC
= 5.0V±10%V, V
SS
= 0V)
60
Parameter
Random read/write cycle time
Access time from RAS*
Access time from CAS*
Access time from column address
Output buffer turn-off time
Transition time (rise and fall)
RAS* precharge time
RAS* pulse width
RAS* hold time
CAS* hold time
CAS* pulse width
RAS* to CAS* delay time
RAS* to column address delay time
CAS* to RAS* precharge time
Row address set-up time
Row address hold time
Column address set-up time
Column address hold time
Column address to RAS* lead time
Read command set-up time
Read command hold time to CAS*
Read command hold time to RAS*
Write command hold time
Write command pulse width
Write command to RAS* lead time
Write command to CAS* lead time
Data-in set-up time
Data-in hold time
(2048 cycles)
Refresh period
(4096 cycles)
Write command set-up time
CAS* set-up time (CBR refresh)
CAS* hold time (CBR refresh)
RAS* precharge to CAS* hold time
Access time from CAS* precharge
Hyper Page mode cycle time
CAS* precharge time (Hyper Page)
RAS* pulse width (Hyper Page)
Symbol
Min
t
RC
t
RAC
t
CAC
t
AA
t
OFF
t
T
t
RP
t
RAS
t
RSH
t
CSH
t
CAS
t
RCD
t
RAD
t
CRP
t
ASR
t
RAH
t
ASC
t
CAH
t
RAL
t
RCS
t
RCH
t
RRH
t
WCH
t
WP
t
RWL
t
CWL
t
DS
t
DH
t
REF
t
WCS
t
CSR
t
CHR
t
RPC
t
CPA
t
HPC
t
CP
t
RASP
110
-
-
-
0
3
40
60
15
60
15
20
15
5
0
10
0
12
30
5
0
0
12
10
15
15
0
12
-
-
0
10
10
5
-
25
8
—
Max
-
60
15
30
15
50
-
10000
-
-
10000
45
30
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
32
64
-
-
-
-
35
-
-
200000
Min
130
-
-
-
0
3
50
70
20
70
20
20
15
5
0
10
0
15
35
5
0
0
15
15
20
20
0
15
-
-
0
10
15
5
-
30
10
—
Max
-
70
20
35
17
50
-
10000
-
-
10000
50
35
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
32
64
-
-
-
-
40
-
-
200000
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
12
3, 11
7
1
1
9
9
8
4
10
3, 4
3, 4, 5
3, 10
6
2
70
Unit
Notes
Fujitsu Microelectronics, Inc.
5
MCU
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