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QL4090-2PL84M

Description
FPGA, 320 CLBS, 16000 GATES, CQFP100
Categorysemiconductor    Programmable logic devices   
File Size390KB,22 Pages
ManufacturerETC1
Download Datasheet Parametric View All

QL4090-2PL84M Overview

FPGA, 320 CLBS, 16000 GATES, CQFP100

QL4090-2PL84M Parametric

Parameter NameAttribute value
Number of functions1
Number of terminals100
Maximum operating temperature125 Cel
Minimum operating temperature-55 Cel
Maximum supply/operating voltage3.6 V
Minimum supply/operating voltage3 V
Rated supply voltage3.3 V
Processing package description0.025 INCH PITCH, CERAMIC, MO-113, QFP-100
stateACTIVE
CraftsmanshipCMOS
packaging shapeSQUARE
Package SizeFLATPACK, HEAT SINK/SLUG, GUARD RING
surface mountYes
Terminal formFLAT
Terminal spacing0.6350 mm
terminal coatingNOT SPECIFIED
Terminal locationQUAD
Packaging MaterialsCERAMIC, METAL-SEALED COFIRED
Temperature levelMILITARY
organize320 CLBS, 16000 GATES
Number of configurable logic modules320
Programmable logic typeFIELD PROGRAMMABLE GATE ARRAY
Number of equivalent gate circuits16000
The maximum delay of a CLB module5.25 ns
Military QuickRAM
90,000 Usable PLD Gate QuickRAM Combining Performance, Density
and
Embedded RAM
Military QuickRAM
D
EVICE
H
IGHLIGHTS
Device Highlights
Features
F
EATURES
Total of 316 I/O pins
s
High Performance and High Density
s
s
Up to 90,000 Usable PLD Gates with 316 I/Os
300 MHz 16-bit Counters, 400 MHz Datapaths, 160+
MHz FIFOs
0.35um four-layer metal non-volatile CMOS process for
smallest die sizes
308 bi-directional input/output pins, PCI-compliant for
5.0 volt and 3.3 volt buses for -1/-2/-3/-4 speed grades
8 high-drive input/distributed network pins
s
s
Eight Low-Skew Distributed Networks
s
High Speed Embedded SRAM
s
Up to 22 dual-port RAM modules, organized in user-
configurable 1,152-bit blocks
5ns access times, each port independently accessible
Fast and efficient for FIFO, RAM, and ROM functions
Two array clock/control networks available to the logic
cell flip-flop clock, set and reset inputs - each driven by
an input-only pin
Six global clock/control networks available to the logic
cell F1, clock, set and reset inputs and the input and I/O
register clock, reset and enable inputs as well as the
output enable control - each driven by an input-only or
I/O pin, or any logic cell output or I/O cell feedback
s
s
s
Easy to Use / Fast Development Cycles
s
100% routable with 100% utilization and complete
pin-out stability
Variable-grain logic cells provide high performance and
100% utilization
Comprehensive design tools include high quality Verilog/
VHDL synthesis
High Performance
s
s
s
s
Input + logic cell + output total delays under 6 ns
Data path speeds exceeding 400 MHz
Counter speeds over 300 MHz
FIFO speeds over 160+ MHz
s
s
Advanced I/O Capabilities
s
s
Military Reliability
s
s
Interfaces with both 3.3 volt and 5.0 volt devices
PCI compliant with 3.3V and 5.0V buses for -1/-2
speed grades
Full JTAG boundary scan
Registered I/O cells with individually controlled clocks
and output enables
Device
QL4016
11,520 RAM Bits
Mil-STD-883 and Miil Temp Ceramic
Mil Temp Plastic - Guaranteed -55
°
C to 125
°
C
s
s
Usable
Gates
8,000-
16,000
Package
Max
I/O
70
70
82
118
174
174
174
174
207
223
316
Qualification
Level
M, /883
M
M, /883
M, /883
M
M, /883
M
M, /883
M
M, /883
M
Supply
Voltage
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3V
3.3V
3.3V
3.3V
3.3V
84CPGA
84PLCC
100CQFP
144CPGA
QL4036
16,000-
208PQFP
16,128 RAM bits
25,000
208CQFP
208PQFP
208CQFP
QL4090
36,000-
240PQFP
25,344 RAM bits
60,000
256CPGA
456PBGA
M = Military Temperature (-15 to +125 degrees C)
/888 = MIL STD 883
TABLE 1: Selector Table
Rev A
8-
37
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