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5962-9562411HNC

Description
SRAM Module, 512KX32, 35ns, CMOS, QFP-68
Categorystorage    storage   
File Size281KB,22 Pages
ManufacturerMicrosemi
Websitehttps://www.microsemi.com
Download Datasheet Parametric View All

5962-9562411HNC Overview

SRAM Module, 512KX32, 35ns, CMOS, QFP-68

5962-9562411HNC Parametric

Parameter NameAttribute value
package instructionQFP-68
Reach Compliance Codeunknown
Maximum access time35 ns
Other featuresCONFIGURABLE AS 2M X 8
Spare memory width16
I/O typeCOMMON
JESD-30 codeS-XQFP-F68
JESD-609 codee4
length39.625 mm
memory density16777216 bit
Memory IC TypeSRAM MODULE
memory width32
Number of functions1
Number of terminals68
word count524288 words
character code512000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize512KX32
Output characteristics3-STATE
Package body materialUNSPECIFIED
encapsulated codeQFF
Encapsulate equivalent codeQFL68,1.56SQ
Package shapeSQUARE
Package formFLATPACK
Parallel/SerialPARALLEL
power supply5 V
Certification statusNot Qualified
Filter levelMIL-STD-883
Maximum seat height5.1 mm
Maximum standby current0.04 A
Minimum standby current2 V
Maximum slew rate0.8 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceGOLD
Terminal formFLAT
Terminal pitch1.27 mm
Terminal locationQUAD
width39.625 mm
REVISIONS
LTR
A
DESCRIPTION
Added note to paragraph 1.2.2 and table I regarding the 4 transistor
design. Paragraph 1.3; changed the power dissipation for device types
05-09 from 2.9 W max to 3.3 W max. Table I; changed the I
CC
max limit
for device types 05-09 from 520 mA to 600 mA. Table I; changed the
I
CCDR1
max limit from 12 mA to 28 mA. Figure 1; changed dimension A
minimum from 0.175 inches to 0.115 inches. Redrew entire document . -
sld
Drawing updated to reflect current requirements. -sld
Table I; Changed the maximum limit for COE and CAD tests from 32
pF to 30 pF. -sld
Update drawing to latest requirements of MIL-PRF-38534. -gc
DATE (YR-MO-DA)
00-09-27
APPROVED
Michael Jones
B
C
D
04-03-29
06-02-06
17-10-17
Raymond Monnin
Raymond Monnin
Charles F. Saffle
REV
SHEET
REV
SHEET
D
15
D
16
D
17
D
18
REV
SHEET
PREPARED BY
Gary Zahn
CHECKED BY
Michael C. Jones
APPROVED BY
Kendall A. Cottongim
D
19
D
20
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
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9
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11
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REV STATUS
OF SHEETS
PMIC N/A
STANDARD MICROCIRCUIT
DRAWING
THIS DRAWING IS
AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF
DEFENSE
AMSC N/A
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
http://www.landandmaritime.dla.mil/
MICROCIRCUIT, HYBRID, MEMORY,
DIGITAL, 512K x 32-BIT, STATIC RANDOM
ACCESS MEMORY, CMOS
DRAWING APPROVAL DATE
96-08-09
REVISION LEVEL
D
SIZE
A
SHEET
CAGE CODE
67268
1 OF
20
5962-E037-18
5962-95624
DSCC FORM 2233
APR 97
DISTRIBUTION STATEMENT A. Approved for public release. Distribution is unlimited.

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Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
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