A
PPLICATION
N
OTE
A V A I L A B L E
AN99 • AN115 • AN120 • AN124 • AN133 • AN134 • AN135
Low Noise/Low Power/SPI Bus/256 Taps
X9250
Quad Digitally Controlled Potentiometers (XDCP
™
)
FEATURES
•
•
•
•
•
•
•
•
Four potentiometers in one package
256 resistor taps/pot–0.4% resolution
SPI serial interface
Wiper resistance, 40
Ω
typical @ V
CC
= 5V
Four nonvolatile data registers for each pot
Nonvolatile storage of wiper position
Standby current < 5µA max (total package)
Power supplies
—V
CC
= 2.7V to 5.5V
—V+ = 2.7V to 5.5V
—V– = -2.7V to -5.5V
100K
Ω
, 50K
Ω
total pot resistance
High reliability
—Endurance – 100,000 data changes per bit per
register
—Register data retention – 100 years
24-lead SOIC, 24-lead TSSOP, 24-lead CSP (Chip
Scale Package)
Dual supply version of X9251
DESCRIPTION
The X9250 integrates 4 digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated circuit.
The digitally controlled potentiometer is implemented
using 255 resistive elements in a series array.
Between each element are tap points connected to
the wiper terminal through switches. The position of
the wiper on the array is controlled by the user through
the SPI bus interface. Each potentiometer has
associated with it a volatile Wiper Counter Register
(WCR) and 4 nonvolatile Data Registers (DR0:DR3)
that can be directly written to and read by the user.
The contents of the WCR controls the position of the
wiper on the resistor array though the switches. Power
up recalls the contents of DR0 to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
•
•
•
•
BLOCK DIAGRAM
V
CC
V
SS
V+
V-
R
0
R
1
Wiper
Counter
Register
(WCR)
Pot 0
V
H0
/R
H0
R
0
R
1
Wiper
Counter
Register
(WCR)
V
H2
/R
H2
HOLD
CS
SCK
SO
SI
A0
A1
WP
R
2
R
3
V
L0
/R
L0
V
W0
/R
W0
R
2
R
3
Resistor
Array
Pot 2
V
L2
/R
L2
V
W2
/R
W2
Interface
and
Control
Circuitry
Data
8
V
W1
/R
W1
R
0
R
1
Wiper
Counter
Register
(WCR)
V
H1
/R
H1
R
0
R
1
Wiper
Counter
Register
(WCR)
V
W3
/R
W3
V
H3
/R
H3
R
2
R
3
Resistor
Array
Pot1
V
L1
/R
L1
R
2
R
3
Resistor
Array
Pot 3
V
L3
/R
H3
REV 1.1.5 1/31/03
www.xicor.com
Characteristics subject to change without notice.
1 of 21
X9250
PIN DESCRIPTIONS
Serial Output (SO)
SO is a serial data output pin. During a read cycle,
data is shifted out on this pin. Data is clocked out by
the falling edge of the serial clock.
Serial Input
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.
Serial Clock (SCK)
The SCK input is used to clock data into and out of the
X9250.
Chip Select (CS)
When CS is HIGH, the X9250 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS LOW enables the X9250, placing it
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.
Hold (HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must
be brought LOW while SCK is LOW. To resume
communication, HOLD is brought HIGH, again while
SCK is LOW. If the pause feature is not used, HOLD
should be held HIGH at all times.
Device Address (A
0
–
A
1
)
The address inputs are used to set the least significant
2 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with
the X9250. A maximum of 4 devices may occupy the
SPI serial bus.
Potentiometer Pins
V
H
/R
H
(V
H0
/R
H0
–V
H3
/R
H3
), V
L
/R
L
(V
L0
/R
L0
–V
L3
/R
L3
)
The R
H
and R
L
pins are equivalent to the terminal
connections on a mechanical potentiometer.
REV 1.1.5 1/31/03
V
W
/R
W
(V
W0
/R
W0
–V
W3
/R
W3
)
The wiper pins are equivalent to the wiper terminal of
a mechanical potentiometer.
Hardware Write Protect Input (WP)
The WP pin when LOW prevents nonvolatile writes to
the Data Registers.
Analog Supplies (V+, V-)
The analog supplies V+, V- are the supply voltages for
the XDCP analog section.
PIN CONFIGURATION
SOIC/TSSOP
S0
A0
V
W3
/R
W3
V
H3
/R
H3
V
L3
/R
L3
V+
V
CC
V
L0
/R
L0
V
H0
/R
H0
V
W0
/R
W0
CS
WP
1
2
3
4
5
6
7
8
9
10
11
12
X9250
24
23
22
21
20
19
18
17
16
15
14
13
HOLD
SCK
V
L2
/R
L2
V
H2
/R
L2
V
W2
/R
W2
V–
V
SS
V
W1
/R
W1
V
H1
/R
H1
V
L1
/R
L1
A1
SI
1
A
B
C
D
E
F
CSP
2
3
4
R
W0
CS
A
1
R
L1
R
W1
R
L0
WP SI
V
CC
R
H0
R
H1
V
SS
V+ R
H3
R
H2
V-
R
L3
SO HOLD R
W2
R
W3
A
0
SCK R
L2
Top View–Bumps Down
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Characteristics subject to change without notice.
2 of 21
X9250
PIN NAMES
Symbol
SCK
SI, SO
A
0
-A
1
V
H0
/R
H0–
V
H3
/R
H3
,
V
L0
/R
L0–
V
L3
/R
L3
V
W0
/R
W0–
V
W3
/R
W3
WP
V+,V-
V
CC
V
SS
NC
Description
Serial Clock
Serial Data
Device Address
Potentiometer Pins
(terminal equivalent)
Potentiometer Pins
(wiper equivalent)
Hardware Write Protection
Analog Supplies
System Supply Voltage
System Ground
No Connection
Wiper Counter Register (WCR)
The X9250 contains four Wiper Counter Registers,
one for each XDCP potentiometer. The WCR is
equivalent to a serial-in, parallel-out register/counter
with its outputs decoded to select one of 256 switches
along its resistor array. The contents of the WCR can
be altered in four ways: it may be written directly by the
host via the write Wiper Counter Register instruction
(serial load); it may be written indirectly by transferring
the contents of one of four associated Data Registers
via the XFR Data Register or Global XFR Data
Register instructions (parallel load); it can be modified
one step at a time by the increment/decrement
instruction. Finally, it is loaded with the contents of its
Data Register zero (DR0) upon power-up.
The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9250 is powered-
down. Although the register is automatically loaded
with the value in R0 upon power-up, this may be
different from the value present at power-down.
Data Registers
Each potentiometer has four 8-bit nonvolatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Counter
Register. All operations changing data in one of the
Data Registers is a nonvolatile operation and will take
a maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.
Data Register Detail
(MSB)
D7
NV
D6
NV
D5
NV
D4
NV
D3
NV
D2
NV
D1
NV
(LSB)
D0
NV
DEVICE DESCRIPTION
Serial Interface
The X9250 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS must be
LOW and the HOLD and WP pins must be HIGH
during the entire operation.
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
Array Description
The X9250 is comprised of four resistor arrays. Each
array contains 255 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (V
H
/R
H
and V
L
/R
L
inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(V
W
/R
W
) output. Within each individual array only one
switch may be turned on at a time.
These switches are controlled by a Wiper Counter
Register (WCR). The 8 bits of the WCR are decoded
to select, and enable, one of 256 switches.
REV 1.1.5 1/31/03
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Characteristics subject to change without notice.
3 of 21
X9250
Figure 1. Detailed Potentiometer Block Diagram
(One of Four Arrays)
Serial Data Path
From Interface
Circuitry
Register 0
8
Register 1
8
Parallel
Bus
Input
Wiper
Counter
Register
(WCR)
Serial
Bus
Input
C
o
u
n
t
e
r
D
e
c
o
d
e
V
H
/R
H
Register 2
Register 3
If WCR = 00[H] then V
W
/R
W
= V
L
/R
L
If WCR = FF[H] then V
W
/R
W
= V
H
/R
H
Inc/Dec
Logic
UP/DN
Modified SCK
UP/DN
CLK
V
L
/R
L
V
W
/R
W
Write in Process
The contents of the Data Registers are saved to
nonvolatile memory when the CS pin goes from LOW
to HIGH after a complete write sequence is received
by the device. The progress of this internal write
operation can be monitored by a write in process bit
(WIP). The WIP bit is read with a read status
command.
INSTRUCTIONS
Identification (ID) Byte
The first byte sent to the X9250 from the host,
following a CS going HIGH to LOW, is called the
Identification byte. The most significant four bits of the
slave address are a device type identifier, for the
X9250 this is fixed as 0101[B] (refer to Figure 2).
The two least significant bits in the ID byte select one
of four devices on the bus. The physical device
address is defined by the state of the A
0
-A
1
input pins.
The X9250 compares the serial data stream with the
address input state; a successful compare of both
address bits is required for the X9250 to successfully
continue the command sequence. The A
0
–A
1
inputs
can be actively driven by CMOS input signals or tied to
V
CC
or V
SS
.
The remaining two bits in the slave byte must be set to 0.
REV 1.1.5 1/31/03
Figure 2. Identification Byte Format
Device Type
Identifier
0
1
0
1
0
0
A1
A0
Device Address
Instruction Byte
The next byte sent to the X9250 contains the
instruction and register pointer information. The four
most significant bits are the instruction. The next four
bits point to one of the four pots and, when applicable,
they point to one of four associated registers. The
format is shown below in Figure 3.
Figure 3. Instruction Byte Format
Register
Select
I3
I2
I1
I0
R1
R0
P1
P0
Instructions
Pot Select
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Characteristics subject to change without notice.
4 of 21
X9250
The four high order bits of the instruction byte specify
the operation. The next two bits (R
1
and R
0
) select one
of the four registers that is to be acted upon when a
register oriented instruction is issued. The last two bits
(P1 and P
0
) selects which one of the four
potentiometers is to be affected by the instruction.
Four of the ten instructions are two bytes in length and
end with the transmission of the instruction byte. These
instructions are:
– XFR Data Register to Wiper Counter Register—This
transfers the contents of one specified Data Register
to the associated Wiper Counter Register.
– XFR Wiper Counter Register to Data Register—This
transfers the contents of the specified Wiper Counter
Register to the specified associated Data Register.
– Global XFR Data Register to Wiper Counter Register—
This transfers the contents of all specified Data Reg-
isters to the associated Wiper Counter Registers.
– Global XFR Wiper Counter Register to Data Register—
This transfers the contents of all Wiper Counter Reg-
isters to the specified associated Data Registers.
The basic sequence of the two byte instructions is
illustrated in Figure 4. These two-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the wiper
to this action will be delayed by t
WRL
. A transfer from
the WCR (current wiper position), to a Data Register is
a write to nonvolatile memory and takes a minimum of
t
WR
to complete. The transfer can occur between one of
the four potentiometers and one of its associated
registers; or it may occur globally, where the transfer
occurs between all potentiometers and one associated
register.
Five instructions require a three-byte sequence to
complete. These instructions transfer data between the
host and the X9250; either between the host and one of
the data registers or directly between the host and the
Wiper Counter Register. These instructions are:
– Read Wiper Counter Register—read the current
wiper position of the selected pot,
– Write Wiper Counter Register—change current wiper
position of the selected pot,
– Read Data Register—read the contents of the
selected data register;
– Write Data Register—write a new value to the
selected data register.
– Read Status—This command returns the contents of
the WIP bit which indicates if the internal write cycle
is in progress.
The sequence of these operations is shown in Figure 5
and Figure 6.
The final command is Increment/Decrement. It is
different from the other commands, because it’s length
is indeterminate. Once the command is issued, the
master can clock the selected wiper up and/or down in
one resistor segment steps; thereby, providing a fine
tuning capability to the host. For each SCK clock pulse
(t
HIGH
) while SI is HIGH, the selected wiper will move
one resistor segment towards the V
H
/R
H
terminal.
Similarly, for each SCK clock pulse while SI is LOW, the
selected wiper will move one resistor segment towards
the V
L
/R
L
terminal. A detailed illustration of the sequence
and timing for this operation are shown in Figure 7 and
Figure 8.
REV 1.1.5 1/31/03
www.xicor.com
Characteristics subject to change without notice.
5 of 21
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