21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI49FCT32805
3.3V, 2 x 1:5 CMOS Clock Driver
Features
Low output skew: <270ps
Switching frequency of 133 MHz
Fast output rise/fall time <1.5ns
Low propagation delay <3.0ns
Low input capacitance <6.0pF
Balanced CMOS outputs
Industrial Temperature: 40°C to +85°C
3.3V ±10% operation
Packages available:
20-pin 300-mil wide SOIC (S)
20-pin 150-mil wide QSOP (Q)
20-pin 209-mil wide SSOP (H)
Description
Pericom Semiconductors PI49FCT series of logic circuits are
produced using the Companys advanced submicron CMOS
technology to achieve fast speed, low skew, fast slew rate, and low
propagation delay for most computing and communication
applications.
The PI49FCT32805 are non-inverting drivers. The outputs are
configured into 2 groups of 1-in, 5-out with independent output
enable. Group B has an extra MON output. Excellent output signals
to power and ground ratio minimize power and ground noise, and
also improves output performance.
PI49FCT32805 integrate series damping resistors on all outputs.
PI49FCT32805 Logic Block Diagram
OE
A
5
IN
A
OA
0–4
PI49FCT32805 Product Pin Configuration
VCCA
OA0
OA1
OA2
GNDA
OA3
OA4
GNDQ
OEA
INA
1
20
2
19
3
18
4
17
20-Pin
5
H,Q,S
16
6
15
7
14
8
13
9
12
10
11
V
CCB
OB0
OB1
OB2
GNDB
OB3
OB4
MON
OEB
INB
5
IN
B
OE
B
OB
0–4
MON
Product Pin Description
Pin Name
OE
A,
OE
B
IN
A,
IN
B
OA
N,
OB
N
MON
GND
V
CC
Description
Hi-Z State Output Enable Inputs (Active LOW)
Clock Inputs
Clock Outputs
Monitor Output
Ground
Power
PI49FCT32805 Truth Table
(1)
Inputs
OE
A
, OE
B
L
L
H
H
IN
A
, IN
B
L
H
L
H
Outputs
OA
N
, OB
N
MON
L
L
H
H
Z
L
Z
H
Note:
1. H = High Voltage Level
L = Low Voltage Level
Z = High Impedance
PS8494
08/09/00
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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI49FCT32805
3.3V, 2 x 1:5 CMOS Clock Driver
Capacitance
(T
A
= 25°C, f = 1 MHz)
Parameters
(1)
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
V
IN
= 0V
V
OUT
= 0V
Typ
3.0
Max.
4
6
Units
pF
pF
Note:
1.This parameter is determined by device characterization but is not production tested.
Maximum Ratings -
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ............................................................ 65°C to +150°C
Ambient Temperature with Power Applied ........................... 40°C to +85°C
Supply Voltage to Ground Potential (Inputs & Vcc Only) ...... 0.5V to +4.6V
Supply Voltage to Ground Potential (Outputs & I/O Only) .... 0.5V to +4.6V
DC Input Voltage .................................................................... 0.5V to +4.6V
DC Output Current ............................................................................. 120 mA
Power Dissipation ................................................................................. 0.5W
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
Operating Range
Ambient Temperature = 40°C to +85°C, Vcc = 3.3V ± 0.3V
DC Electrical Characteristics
(Over the Operating Range)
Symbol
V
OH
D e s cription
O utput high voltage
V
CC
= 3.0V
V
IN
= V
IL
or V
IH
O utput low voltage
V
CC
= 3.0V
V
IN
= V
IL
or V
IH
Input high voltage
Input low voltage
Input high current
Input low current
High impedance
output current
Clamp diode voltage
O utput HIGH
(4)
current
O utput LO W
(4)
current
Short circuit
(5)
current
Internal series resistor
I
OH
= 8mA
Te s t Conditions
(1)
M in.
2.4
(3)
2.0
0.5
V
OUT
= V
CC
V
OUT
= GND
25
25
50
Typ.
(2)
3.0
M ax.
Units
V
OL
I
OL
= 12mA
LO W logic
HIGH logic
V
CC
= max., V
IN
= V
CC
V
CC
= max., V
IN
= GND
V
CC
= max, all
outputs disabled
V
CC
= min., I
IN
= 18mA
V
OUT
= 1.5V, V
IN
= V
IL
or V
IH
V
CC
= 3.3V
V
OUT
= 1.5V, V
IN
= V
IL
or V
IH
V
CC
= 3.3V
V
CC
= max.
V
OUT
= GND
0.4
0.9
55
45
100
22
0.5
V
CC
- 0.2
0.8
1
1
1
1
1.2
80
90
180
V
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
V
IK
I
OH
I
OL
I
os
Rs
µA
V
mA
O hm
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 3.3V, +25°C ambient and maximum loading.
3. V
OH
= V
CC
0.6V at rated current.
4. This parameter is determined by device characterization but is not production tested.
5. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
2
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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI49FCT32805
3.3V, 2 x 1:5 CMOS Clock Driver
Power Supply Characteristics
Parameters Description
I
CC
∆I
CC
I
CCD
Quiescent Power
Supply Current
Supply Current per
Inputs @ TTL HIGH
Supply Current per
Input per MHz
(4)
V
CC
= Max.
V
CC
= Max.
V
CC
= Max.,
Outputs Open
OE
A
or OE
B
= GND
Per Output Toggling
50% Duty Cycle
V
CC
= Max.,
Outputs Open
f
O
= 10 MH
Z
50% Duty Cycle
OE
A
or OE
B
= GND
Mon. Outputs Toggling
V
CC
= Max.,
Outputs Open
f
O
= 2.5 MH
Z
50% Duty Cycle
OE
A
or OE
B
= GND
Eleven Outputs Toggling
Test Conditions
(1)
V
IN
= GND or V
CC
V
IN
= V
CC
– 0.6V
(3)
V
IN
= V
CC
V
IN
= GND
Min.
—
—
—
Typ
(2)
0.1
110
0.09
Max.
30
300
0.16
Units
µA
µA
mA/
MH
Z
I
C
V
IN
= V
CC
V
IN
= GND
V
IN
= V
CC
– 0.6V
V
IN
= GND
V
IN
= V
CC
V
IN
= GND
V
IN
= V
CC
– 0.6V
V
IN
= GND
—
1.3
9.0
(5)
—
1.3
10.0
(5)
mA
—
4.4
6.0
(5)
—
4.4
7.0
(5)
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device.
2. Typical values are at V
CC
= 3.3V, +25°C ambient.
3. Per TTL driven input (V
IN
= V
CC
0.6V); all other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
C
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
O
N
O
)
I
CC
= Quiescent Current
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= V
CC
0.6V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
O
= Output Frequency
N
O
= Number of Outputs at f
O
All currents are in milliamps and all frequencies are in megahertz.
3
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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI49FCT32805
3.3V, 2 x 1:5 CMOS Clock Driver
Switching Characteristics over Operating Range
Symbol
De s cription
Propagation Delay
A to Bn
(3)
Rise/Fall Time
(2)
0.5V - 2.0V
Pulse Skew
(2)
Condition
15pF
M ax.
(2)
3.0
Units
Switch Position
Te s t
Disable LOW
Enable LOW
Disable HIGH
Enable HIGH
All Other Inputs
Switch
6V
GND
Open
t
PLH
t
PHL
t
R/
t
F
t
SK (p)
15pF
Same Output
Same Package,
Same Bank
Same Device,
Same Bank
15pF
15pF
1.5
0.35
0.27
0.55
5.2
133
MHz
ns
t
SK (o)
Output Skew
(2)
t
SK (t)
Package Skew
(2)
Definitions:
CL
= Load capacitance: includes jig and probe capacitance.
RT
= Termination resistance: should be equal to ZOUT of
the Pulse Generator.
t
ZL
, t
ZH,
Enable/Disable Time
t
LZ
, t
HZ
F
M A X
Input Frequency
Note:
1. Lumped load, C
L
= 15pF
2. These parameters are guaranteed by design
3. Minimum propagation delay of 1.5ns is guaranteed but not tested.
Tests Circuits for F
IN
>100 MHz
(2)
V
CC
Enable/Disable Time Test Set-Up
6V
Pulse
Generator
f = 125MHz
50Ω
Sw
D.U.T.
V
CC
500Ω
C
L
= 15pF
Pulse
Generator
R
T
D.U.T.
C
L
= 15pF
500Ω
R
T
=
Termination resistance, should be equal to
Z
OUT
of the
pulse generators.
4
PS8494
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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI49FCT32805
3.3V, 2 x 1:5 CMOS Clock Driver
SWITCHING WAVEFORMS
Propagation Delay
3V
Input
t
PLH
Output
t
PHL
V
OH
1.5V
V
OL
1.5V
0V
Output Skew t
SK
(o)
3V
Input
tPLHx
Ox
tSK(o)
tSK(o)
1.5V
0V
tPHLx
VOH
1.5V
VOL
VOH
Oy
1.5V
tPLHy
VOL
tPHLy
Enable and Disable Times
Enable
OE
Disable
3V
1.5V
0V
t
PZL
Output
Normally
Low
3.0V
Switch
Closed
1.5V
0.3V
t
PHZ
0.3V
1.5V
0V
0V
V
OH
V
OL
t
PLZ
3.0V
tSK(o) = | tPLHy – tPLHx | or | tPHLy – tPHLx |
Pulse Skew t
SK
(p)
3V
Input
tPLH
Output
tPHL
VOH
1.5V
VOL
tSK(p) = | tPHL – tPLH |
1.5V
0V
t
PZH
Output
Normally
High
Switch
Open
Package Skew t
SK
(t)
3V
Input
tPLH1
Package 1
Output
tSK(t)
tSK(t)
1.5V
0V
tPHL1
VOH
1.5V
VOL
VOH
Package 2
Output
tPLH2
1.5V
VOL
tPHL2
tSK(t) = | tPLH2 – tPLH1 | or | tPHL2 – tPHL1 |
5
PS8494
08/09/00
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