SN74LS298
Quad 2-Input Multiplexer
with Storage
The SN74LS298 is a Quad 2-Port Register. It is the logical
equivalent of a quad 2-input multiplexer followed by a quad 4-bit
edge-triggered register. A Common Select input selects between two
4-bit input ports (data sources.) The selected data is transferred to the
output register synchronous with the HIGH to LOW transition of the
Clock input.
The LS298 is fabricated with the Schottky barrier process for high
speed and is completely compatible with all ON Semiconductor TTL
families.
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LOW
POWER
SCHOTTKY
•
•
•
•
Select From Two Data Sources
Fully Edge-Triggered Operation
Typical Power Dissipation of 65 mW
Input Clamp Diodes Limit High Speed Termination Effects
16
GUARANTEED OPERATING RANGES
Symbol
V
CC
T
A
I
OH
I
OL
Parameter
Supply Voltage
Operating Ambient
Temperature Range
Output Current – High
Output Current – Low
Min
4.75
0
Typ
5.0
25
Max
5.25
70
– 0.4
8.0
Unit
V
°C
mA
mA
1
PLASTIC
N SUFFIX
CASE 648
16
1
SOIC
D SUFFIX
CASE 751B
ORDERING INFORMATION
Device
SN74LS298N
SN74LS298D
Package
16 Pin DIP
16 Pin
Shipping
2000 Units/Box
2500/Tape & Reel
©
Semiconductor Components Industries, LLC, 1999
1
December, 1999 – Rev. 6
Publication Order Number:
SN74LS298/D
SN74LS298
CONNECTION DIAGRAM DIP
(TOP VIEW)
V
CC
16
Q
a
15
Q
b
14
Q
c
13
Q
d
12
CP
11
S
10
I
0c
9
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
1
I
1b
2
I
1a
3
I
0a
4
I
0b
5
I
1c
6
I
1d
7
I
0d
8
GND
LOADING
(Note a)
PIN NAMES
S
CP
I
0a
– I
0d
I
1a
– I
1d
Q
a
– Q
d
Common Select Input
Clock (Active LOW Going Edge) Input
Data Inputs from Source 0
Data Inputs from Source 1
Register Outputs
HIGH
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
LOW
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40
m
A HIGH/1.6 mA LOW.
LOGIC SYMBOL
3
2
4
1
9
5
7 6
I
0a
I
1a
I
0b
I
1b
I
0c
I
1c
I
0d
I
1d
10
11
S
CP
Q
a
15
Q
b
14
Q
c
13
Q
d
12
V
CC
= PIN 16
GND = PIN 8
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2
SN74LS298
LOGIC OR BLOCK DIAGRAM
I
1a
2
I
0a
3
I
1b
1
I
0b
4
I
1c
5
I
0c
9
I
1d
6
I
0d
7
S
10
CP
11
R
CP
S Q
a
15
R
CP
S Q
b
14
R
CP
S Q
c
13
R
CP
S Q
d
12
V
CC
= PIN 16
GND = PIN 8
= PIN NUMBERS
Q
a
Q
b
Q
c
Q
d
FUNCTIONAL DESCRIPTION
The LS298 is a high speed Quad 2-Port Register. It selects
four bits of data from two sources (ports)under the control
of a Common Select Input (S). The selected data is
transferred to the 4-bit output register synchronous with the
HIGH to LOW transition of the Clock input (CP). The 4-bit
output register is fully edge-triggered. The Data inputs (I)
and Select input (S) must be stable only one setup time prior
to the HIGH to LOW transition of the clock for predictable
operation.
TRUTH TABLE
INPUTS
S
I
I
h
h
I
0
I
h
X
X
I
1
X
X
I
h
OUTPUT
Q
L
H
L
H
L = LOW Voltage Level
H = HIGH Voltage Level
X = Don’t Care
I = LOW Voltage Level one setup time prior to the HIGH to LOW clock transition.
h = HIGH Voltage Level one setup time prior to the HIGH to LOW clock transition.
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3
SN74LS298
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
V
IH
V
IL
V
IK
V
OH
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
2.7
– 0.65
3.5
0.25
V
O
OL
Output LOW Voltage
0.35
I
IH
I
IL
I
OS
I
CC
Input HIGH Current
0.1
Input LOW Current
Short Circuit Current (Note 1)
Power Supply Current
– 20
– 0.4
– 100
21
0.5
20
V
µA
mA
mA
mA
mA
I
OL
= 8.0 mA
0.4
Min
2.0
0.8
– 1.5
Typ
Max
Unit
V
V
V
V
V
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
Guaranteed Input LOW Voltage for
All Inputs
V
CC
= MIN, I
IN
= – 18 mA
V
CC
= MIN, I
OH
= MAX, V
IN
= V
IH
or V
IL
per Truth Table
I
OL
= 4.0 mA
V
CC
= V
CC
MIN,
V
IN
= V
IL
or V
IH
per Truth Table
V
CC
= MAX, V
IN
= 2.7 V
V
CC
= MAX, V
IN
= 7.0 V
V
CC
= MAX, V
IN
= 0.4 V
V
CC
= MAX
V
CC
= MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS
(T
A
= 25°C, V
CC
= 5.0 V)
Limits
Symbol
t
PLH
t
PHL
Parameter
Propagation Delay,
g
y
Clock to Output
Min
Typ
18
21
Max
27
32
Unit
ns
ns
Test Conditions
V
CC
= 5.0 V,
C
L
= 15 pF
AC SET-UP REQUIREMENTS
(T
A
= 25°C, V
CC
= 5.0 V)
Limits
Symbol
t
W
t
s
t
s
t
h
t
h
Parameter
Clock Pulse Width
Data Setup Time
Select Setup Time
Data Hold Time
Select Hold Time
Min
20
15
25
5.0
0
Typ
Max
Unit
ns
ns
ns
ns
V
CC
= 5.0 V
Test Conditions
DEFINITIONS OF TERMS
SETUP TIME (t
s
) — is defined as the minimum time
required for the correct logic level to be present at the logic
input prior to the clock transition from LOW to HIGH in
order to be recognized and transferred to the outputs.
HOLD TIME (t
h
) — is defined as the minimum time
following the clock transition from LOW to HIGH that the
logic level must be maintained at the input in order to ensure
continued recognition. A negative HOLD TIME indicates
that the correct logic level may be released prior to the clock
transition from LOW to HIGH and still be recognized.
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4
SN74LS298
AC WAVEFORMS
I
0
I
1
*
t
s(L)
CP
1.3 V
t
PHL
Q
1.3 V
t
W(H)
t
PLH
1.3 V
Q
Q = I
0
Q = I
1
1.3 V
t
h(L)
t
W(L)
t
s(H)
1.3 V
1.3 V
t
h(H)
t
s(L)
CP
1.3 V
S*
1.3 V
t
h(L) = 0
1.3 V
t
h(H) = 0
t
s(H)
1.3 V
*The shaded areas indicate when the input is permitted to
*change
for predictable output performance.
Figure 1.
Figure 2.
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