EURO
QUARTZ
11.4 x 9.6 x 2.5mm 6 pad SMD
DESCRIPTION
HDF62 series LVDS output oscillators cover the frequency range
38MHz to 640MHz. The design contains a high 'Q' fundamental
crystal and utilizes a low jitter multiplier circuit. Integrated phase jitter
is 0.5ps maximum.
SPECIFICATION
Frequency Range:
38.0MHz to 640.0MHz
Output Logic
LVDS
Phase Noise:
See table
Frequency Stability:
See table
Operating Temp Range
Commercial:
-10° to +70°C
Industrial:
-40° to +85°C
Input Voltage:
+2.5V or +3.3VDC ±5%
Output Logic
High '1' V
OH
:
1.4V typical, 1.6V max.
OL
:
Low '0' V
0.9V min., 1.1V typical
OD
:
Differential Output Voltage V
247mV min., 355mV typ.,
454mV max. Output 1 - Output 2
OD
: -50mV min., 50mV max.
Differential Output Error dV
Output Offset Voltage V
OS
:
1.125V min., 1.20V typ., 1.375V max.
Offset Magnitude Error dV
OS
:
0mV min., 3mV typ., 25mV max.
Rise/Fall Times:
0.7ns typical, 1.0ns max.
(20% to 80% of LVDS waveform)
Current Consumption (15pF load):
38MHz to 100MHz:
45mA max.
100.01 to 320MHz:
60mA max.
320.01 to 640MHz:
70mA max.
Load:
50W from each output
Start-up Time:
5ms typ., 10ms max.
Duty Cycle:
50%±5% (at 1.5V)
Drive Capability:
100 Ohms between outputs
Input Static Discharge Prot:
2kV min.
Storage Temperature Range:
-55°C to +150°C
Ageing:
±3ppm per year max., ±2ppm
thereafter. At T amb +25°C
Enable/Disable
No connection:
Both outputs enabled
Disable:
Both outputs are disabled when
control pad is taken below 0.3V
referenced to ground. Oscillator is
always 'on'. (Special request -
oscillator is off when disabled.)
Enable:
Both Outputs are enabled when
control pad is taken above 0.7 Vcc
referenced to ground.
ABSOLUTE MAXIMUM RATINGS
(Permanent
damage may be caused if operated beyond these limits.)
Supply Voltage Vdd:
+4.6VDC max.
Input Voltage Vi:
Vss -0.5 min., VDD +0.5V max.
Input Voltage Vo:
Vss -0.5 min., Vdd +0.5V max.
STABILITY OVER TEMPERATURE RANGE
Stability
±ppm
25
50
100
25
50
100
Temperature Range Order Code
°C
-10 to +70
-10 to +70
-10 to +70
-40 to +85
-40 to +85
-40 to +85
A
B
C
D
E
F
HDF62 LVDS OSCILLATORS
38.0MHz to 640.0MHz
OUTLINE & DIMENSIONS
PHASE NOISE
(156.250MHz)
Offset
10Hz
100Hz
1kHz
10kHz
100kHz
1MHz
10MHz
dBc/Hz
-62
-92
-120
-132
-128
-140
-150
JITTER
(156.520MHz)
Typ.
Max.
Integrated Phase Jitter: 0.4ps 0.5ps
(12kHz to 20MHz)
Period Jitter:
3.0ps 5.0ps
(RMS)
Period Jitter:
20ps 30ps
(peak to peak)
PART NUMBERS
HDF62 oscillator part numbers are derived as follows:
Example:
Supply Voltage
25 = 2.5VDC
3 = 3.3VDC
Series Designation
Package Style
621 or 622
Stability Code
(See table)
Frequency
3HDF621-A-250.000
EUROQUARTZ LIMITED Blacknell Lane CREWKERNE Somerset UK TA18 7HE
Tel: +44 (0)1460 230000 Fax: +44 (0)1460 230001 info@euroquartz.co.uk www.euroquartz.co.uk
FPGA/CPLD
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