IS61NLF204818B-7.5B3 datasheet, PDF

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IS61NLF204818B-7.5B3: DescriptionZBT SRAM, 2MX18, 7.5ns, CMOS, PBGA165, 15 X 13 MM, PLASTIC, TFBGA-165; Categorystorage storage; File Size1MB，37 Pages; ManufacturerISSI(Integrated Silicon Solution Inc.); Websitehttp://www.issi.com/

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IS61NLF204818B-7.5B3 Overview

ZBT SRAM, 2MX18, 7.5ns, CMOS, PBGA165, 15 X 13 MM, PLASTIC, TFBGA-165

IS61NLF204818B-7.5B3 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Parts packaging code	BGA
package instruction	TBGA, BGA165,11X15,40
Contacts	165
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	7.5 ns
Maximum clock frequency (fCLK)	117 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B165
length	15 mm
memory density	37748736 bit
Memory IC Type	ZBT SRAM
memory width	18
Number of functions	1
Number of terminals	165
word count	2097152 words
character code	2000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	2MX18
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TBGA
Encapsulate equivalent code	BGA165,11X15,40
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE
Parallel/Serial	PARALLEL
power supply	2.5/3.3,3.3 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum standby current	0.115 A
Minimum standby current	3.14 V
Maximum slew rate	0.24 mA
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	13 mm

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IS61(64)NLF102436B/IS61(64)NVF/NVVF102436B

IS61(64)NLF204818B/IS61(64)NVF/NVVF204818B

1M x 36, 2M x 18

36Mb, FLOW THROUGH 'NO WAIT' STATE BUS SRAM

FEATURES

• 100 percent bus utilization

• No wait cycles between Read and Write

• Internal self-timed write cycle

• Individual Byte Write Control

• Single Read/Write control pin

• Clock controlled, registered address,

data and control

• Interleaved or linear burst sequence control us-

ing MODE input

• Three chip enables for simple depth expansion

and address pipelining

• Power Down mode

• Common data inputs and data outputs

•

CKE

pin to enable clock and suspend operation

• JEDEC 100-pin TQFP, 119-ball PBGA, and 165-

ball PBGA packages

• Power supply:

NLF: V

3.3V (± 5%), V

ddq

3.3V/2.5V (± 5%)

NVF: V

2.5V (± 5%), V

ddq

2.5V (± 5%)

NVVF: V

1.8V (± 5%), V

ddq

1.8V (± 5%)

• JTAG Boundary Scan for PBGA packages

• Industrial temperature available

• Lead-free available

ADVANCED INFORMATION

FEBRUARY 2013

DESCRIPTION

The 72 Meg product family features high-speed, low-power

synchronous static RAMs designed to provide a burstable,

high-performance, 'no wait' state, device for networking

and communications applications. They are organized as

1,048,476 words by 36 bits and 2,096,952 words by 18

bits, fabricated with

ISSI

's advanced CMOS technology.

Incorporating a 'no wait' state feature, wait cycles are

eliminated when the bus switches from read to write, or

write to read. This device integrates a 2-bit burst counter,

high-speed SRAM core, and high-drive capability outputs

into a single monolithic circuit.

All synchronous inputs pass through registers are controlled

by a positive-edge-triggered single clock input. Operations

may be suspended and all synchronous inputs ignored

when Clock Enable,

CKE

is HIGH. In this state the internal

device will hold their previous values.

All Read, Write and Deselect cycles are initiated by the ADV

input. When the ADV is HIGH the internal burst counter

is incremented. New external addresses can be loaded

when ADV is LOW.

Write cycles are internally self-timed and are initiated

by the rising edge of the clock inputs and when

LOW. Separate byte enables allow individual bytes to be

written.

A burst mode pin (MODE) defines the order of the burst

sequence. When tied HIGH, the interleaved burst sequence

is selected. When tied LOW, the linear burst sequence is

selected.

FAST ACCESS TIME

Symbol

Parameter

Clock Access Time

Cycle Time

Frequency

6.5

7.5

133

7.5

8.5

117

Units

MHz

liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on

any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause

failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written

assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc. — www.issi.com —

1-800-379-4774

Rev. 00C

02/20/2013

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