The SN54 / 74LS112A dual JK flip-flop features individual J, K, clock, and
asynchronous set and clear inputs to each flip-flop. When the clock goes
HIGH, the inputs are enabled and data will be accepted. The logic level of the
J and K inputs may be allowed to change when the clock pulse is HIGH and
the bistable will perform according to the truth table as long as minimum set-up
and hold time are observed. Input data is transferred to the outputs on the
negative-going edge of the clock pulse.
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
LOW POWER SCHOTTKY
LOGIC DIAGRAM
(Each Flip-Flop)
J SUFFIX
CERAMIC
CASE 620-09
16
1
Q
5(9)
6(7)
Q
CLEAR (CD)
15(14)
J
3(11)
1(13)
CLOCK (CP)
4(10)
K
2(12)
SET (SD)
16
1
N SUFFIX
PLASTIC
CASE 648-08
16
1
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
MODE SELECT — TRUTH TABLE
INPUTS
OPERATING MODE
SD
Set
Reset (Clear)
*Undetermined
Toggle
Load “0” (Reset)
Load “1” (Set)
Hold
L
H
L
H
H
H
H
CD
H
L
L
H
H
H
H
J
X
X
X
h
l
h
l
K
X
X
X
h
h
l
l
Q
H
L
H
q
L
H
q
Q
L
H
H
q
H
L
q
OUTPUTS
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
LOGIC SYMBOL
4
10
3
J
CP
SD
Q
5
11
J
CP
SD
Q
9
1
13
Q
6
12
* Both outputs will be HIGH while both SD and CD are LOW, but the output states
are unpredictable if SD and CD go HIGH simultaneously.
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Don’t Care
l, h (q) = Lower case letters indicate the state of the referenced input (or output)
l, h (q) =
one set-up time prior to the HIGH to LOW clock transition.
2
K
CD
K
CD
Q
7
15
14
VCC = PIN 16
GND = PIN 8
FAST AND LS TTL DATA
5-185
SN54/74LS112A
GUARANTEED OPERATING RANGES
Symbol
VCC
TA
IOH
IOL
Supply Voltage
Operating Ambient Temperature Range
Output Current — High
Output Current — Low
Parameter
54
74
54
74
54, 74
54
74
Min
4.5
4.75
– 55
0
Typ
5.0
5.0
25
25
Max
5.5
5.25
125
70
– 0.4
4.0
8.0
Unit
V
°C
mA
mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
VIH
VIL
VIK
VOH
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54
74
54, 74
VOL
Output LOW Voltage
74
J, K
Set, Clear
Clock
IIH
Input HIGH Current
J, K
Set, Clear
Clock
J, K
Clear, Set, Clk
– 20
0.35
0.5
20
60
80
0.1
0.3
0.4
– 0.4
– 0.8
– 100
6.0
V
µA
2.5
2.7
54
74
– 0.65
3.5
3.5
0.25
0.4
Min
2.0
0.7
0.8
– 1.5
V
V
V
V
Typ
Max
Unit
V
V
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
Guaranteed Input LOW Voltage for
All Inputs
VCC = MIN, IIN = – 18 mA
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
IOL = 4.0 mA
IOL = 8.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
VCC = MAX, VIN = 2.7 V
mA
VCC = MAX, VIN = 7.0 V
IIL
IOS
ICC
Input LOW Current
mA
mA
mA
VCC = MAX, VIN = 0.4 V
VCC = MAX
VCC = MAX
Short Circuit Current (Note 1)
Power Supply Current
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS
(TA = 25°C, VCC = 5.0 V)
Limits
Symbol
fMAX
tPLH
tPHL
Parameter
Maximum Clock Frequency
Propagation Delay, Clock
Clear, Set to Output
Min
30
Typ
45
15
15
20
20
Max
Unit
MHz
ns
ns
VCC = 5.0 V
CL = 15 pF
Test Conditions
AC SETUP REQUIREMENTS
(TA = 25°C, VCC = 5.0 V)
Limits
Symbol
tW
tW
ts
th
Parameter
Clock Pulse Width High
Clear, Set Pulse Width
Setup Time
Hold Time
Min
20
25
20
0
Typ
Max
Unit
ns
ns
ns
ns
VCC = 5.0 V
Test Conditions
FAST AND LS TTL DATA
5-186
-A-
Case 751B-03 D Suffix
16-Pin Plastic
SO-16
NOTES:
1.
DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2.
3.
CONTROLLING DIMENSION: MILLIMETER.
DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4.
MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5.
751B 01 IS OBSOLETE, NEW STANDARD
751B 03.
16
9
-B-
1
8
P
8 PL
0.25 (0.010)
M
B
M
R X 45°
G
-T-
D
16 PL
0.25 (0.010)
M
C
SEATING
PLANE
K
T
B
S
M
F
J
A
S
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
3.80
1.35
0.35
0.40
10.00
4.00
1.75
0.49
1.25
INCHES
MIN
MAX
0.386
0.150
0.054
0.014
0.016
0.393
0.157
0.068
0.019
0.049
1.27 BSC
0.19
0.10
0
0.25
0.25
7
0.050 BSC
0.008
0.004
0
0.009
0.009
7
°
°
°
°
5.80
0.25
6.20
0.50
0.229
0.010
0.244
0.019
Case 648-08 N Suffix
16-Pin Plastic
-A-
16
9
NOTES:
1.
DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2.
3.
CONTROLLING DIMENSION: INCH.
DIMENSION L" TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4.
DIMENSION B" DOES NOT INCLUDE MOLD
FLASH.
5.
6.
ROUNDED CORNERS OPTIONAL.
648 01 THRU 07 OBSOLETE, NEW STANDARD
648 08.
B
1
8
F
S
C
-T-
K
SEATING
PLANE
L
H
G
D
16 PL
0.25 (0.010)
M
J
M
T
A
M
DIM
A
B
C
D
F
G
H
J
K
L
M
S
MILLIMETERS
MIN
MAX
18.80
6.35
3.69
0.39
1.02
19.55
6.85
4.44
0.53
1.77
INCHES
MIN
MAX
0.740
0.250
0.145
0.015
0.040
0.770
0.270
0.175
0.021
0.070
2.54 BSC
1.27 BSC
0.21
2.80
7.50
0
0.38
3.30
7.74
10
0.100 BSC
0.050 BSC
0.008
0.110
0.295
0
0.015
0.130
0.305
10
°
°
°
°
0.51
1.01
0.020
0.040
-A-
16
9
Case 620-09 J Suffix
16-Pin Ceramic Dual In-Line
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
-B-
1
8
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIM F MAY NARROW TO 0.76 (0.030) WHERE
THE LEAD ENTERS THE CERAMIC BODY.
C
L
5. 620 01 THRU 08 OBSOLETE, NEW STANDARD
620 09.
-T-
SEATING
PLANE
K
E
F
D
16 PL
0.25 (0.010)
M
N
G
T
A
S
M
J
16 PL
0.25 (0.010)
M
T
B
S
DIM
A
B
C
D
E
F
G
J
K
L
M
N
MILLIMETERS
MIN
MAX
19.05
6.10
19.55
7.36
4.19
0.39
0.53
INCHES
MIN
MAX
0.750
0.240
0.770
0.290
0.165
0.015
0.021
1.27 BSC
1.40
1.77
0.050 BSC
0.055
0.070
2.54 BSC
0.23
0.27
5.08
7.62 BSC
0
0.100 BSC
0.009
0.011
0.200
0.300 BSC
0
°
15
°
°
15
°
0.39
0.88
0.015
0.035
FAST AND LS TTL DATA
5-187
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different
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