The Vishay Siliconix SiC401A/B an advanced stand-alone
synchronous buck regulator featuring integrated power
MOSFETs, bootstrap switch, and a programmable LDO in a
space-saving PowerPAK MLP55-32L pin package.
The SiC401A/B is capable of operating with all ceramic
solutions and switching frequencies up to 1 MHz. The
programmable frequency, synchronous operation and
selectable power-save allow operation at high efficiency
across the full range of load current. The internal LDO may
be used to supply 5 V for the gate drive circuits or it may be
bypassed with an external 5 V for optimum efficiency and
used to drive external n-channel MOSFETs or other loads.
Additional features include cycle-by-cycle current limit,
voltage soft-start, under-voltage protection, programmable
over-current protection, soft shutdown and selectable
power-save. The Vishay Siliconix SiC401A/B also provides
an enable input and a power good output.
FEATURES
High efficiency > 93 %
15 A continuous output current capability
Integrated bootstrap switch
Programmable 200 mA LDO with bypass logic
Temperature compensated current limit
All ceramic solution enabled
Pseudo fixed-frequency adaptive on-time control
Programmable input UVLO threshold
Independent enable pin for switcher and LDO
Selectable ultra-sonic power-save mode (SiC401A)
Selectable power-save mode (SiC401B)
Programmable soft-start and soft-shutdown
1 % internal reference voltage
Power good output
Over-voltage and under-voltage protections
PowerCAD Simulation software available at
www.vishay.com/power-ics/powercad-list/
• Material categorization: for definitions of compliance
please see
www.vishay.com/doc?99912
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PRODUCT SUMMARY
Input Voltage Range
Output Voltage Range
Operating Frequency
Continuous Output Current
Peak Efficiency
Package
3 V to 17 V
0.6 V to V
IN
x 0.75
a
200 kHz to 1 MHz
15 A
93 %
PowerPAK MLP55-32L
APPLICATIONS
•
•
•
•
•
•
Notebook, desktop and server computers
Digital HDTV and digital consumer applications
Networking and telecommunication equipment
Printers, DSL, and STB applications
Embedded applications
Point of load power supplies
Note
a. See “High Output Voltage Operation” section
TYPICAL APPLICATION CIRCUIT AND PACKAGE OPTIONS
EN/PSV (Tri-State)
LDO_EN
EN\PSV
P
GOOD
V
OUT
A
GND
ENL
T
ON
P
GOOD
I
LIM
32 31 30 29 28 27 26 25
LX
LX
FB
V
OUT
V
DD
A
GND
FBL
V
IN
V
IN
1
2
3
4
5
6
24
LX
LX
P
GND
P
GND
P
GND
P
GND
P
GND
P
GND
V
OUT
PAD 1
A
GND
PAD 3
PAD 2
V
IN
10
11
23
22
21
20
19
18
17
LX
SS
7
BST
8
NC
12
LX
13
NC
14
Typical Application Circuit for SiC401A/B (PowerPAK MLP5x5-32L)
S14-2048-Rev. D, 13-Oct-14
Document Number: 63835
1
For technical questions, contact:
powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
P
GND
15
P
GND
V
IN
V
IN
V
IN
16
9
SiC401A, SiC401BCD
www.vishay.com
FUNCTIONAL BLOCK DIAGRAM
PGOOD
26
VDD
EN/PSV
29
VDD
Bootstrap
Switch
AGND
D
VDD
DL
SS
7
Soft Start
Hi-side
MOSFET
B
FB
1
FB Comparator
28
TON
31
Zero Cross Detector
VOUT
2
Bypass Comparator
Valley Current Limit
VDD
VDD
3
Y
B
VLDO Switchover MUX
FBL
5
32
ENL
A = connected to pins 6, 9-11, PAD 2
B = connected to pins 23-25, PAD 3
C = connected to pins 15-22
D = connect to pins 4, 30, PAD 1
LDO
14
NC
A
V
IN
27
ILIM
C
PGND
DL
Lo-side
MOSFET
LXS
On- time
-
Generator
Gate Drive
Control
VDD
13
LX
LXBST
12
NC
Reference
Control & Status
8
BST
VIN
A
V
IN
Vishay Siliconix
SiC401A/B Functional Block Diagram
PIN CONFIGURATION
EN\PSV
P
GOOD
A
GND
ENL
tON
I
LIM
LX
LX
32 31 30 29 28 27 26 25
FB
V
OUT
VDD
A
GND
FBL
V
IN
SS
BST
1
2
3
4
5
6
7
8
V
IN
10
V
IN
11
NC 12
LX 13
NC 14
P
GND
15
P
GND
16
V
IN
9
24
PAD 1
A
GND
PAD 3
LX
PAD 2
19
V
IN
18
17
23
22
21
20
LX
LX
P
GND
P
GND
P
GND
P
GND
P
GND
P
GND
SiC401A/B Pin Configuration (Top View)
S14-2048-Rev. D, 13-Oct-14
Document Number: 63835
2
For technical questions, contact:
powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiC401A, SiC401BCD
www.vishay.com
Vishay Siliconix
PIN DESCRIPTION
PIN NUMBER
1
2
3
4, 30, PAD 1
5
6, 9 to 11, PAD 2
7
8
12, 14
13
23 to 25, PAD3
15 to 22
26
27
28
29
31
32
SYMBOL
FB
V
OUT
V
DD
A
GND
FBL
V
IN
SS
BST
NC
LXBST
LX
P
GND
P
GOOD
I
LIM
LXS
EN/PSV
t
ON
ENL
DESCRIPTION
Feedback input for switching regulator used to program the output voltage - connect to an external
resistor divider from V
OUT
to A
GND
.
Switcher output voltage sense pin - also the input to the internal switch-over between V
OUT
and
V
LDO
. The voltage at this pin must be less than or equal to the voltage at the V
DD
pin.
Bias supply for the IC - when using the internal LDO as a bias power supply, V
DD
is the LDO output.
When using an external power supply as the bias for the IC, the LDO output should be disabled.
Analog ground
Feedback input for the internal LDO - used to program the LDO output. Connect to an external
resistor divider from V
DD
to A
GND
.
Input supply voltage
The soft start ramp will be programmed by an internal current source charging a capacitor on this
pin.
Bootstrap pin - connect a capacitor of at least 100 nF from BST to LX to develop the floating supply
for the high-side gate drive.
No connection
LX Boost - connect to the BST capacitor.
Switching (phase) node
Power ground
Open-drain power good indicator - high impedance indicates power is good. An external pull-up
resistor is required.
Current limit sense pin - used to program the current limit by connecting a resistor from I
LIM
to LXS.
LX sense - connects to R
ILIM
Enable/power save input for the switching regulator - connect to A
GND
to disable the switching
regulator, connect to V
DD
to operate with power-save mode and float to operate in forced
continuous mode.
On-time programming input - set the on-time by connecting through a resistor to A
GND
Enable input for the LDO - connect ENL to A
GND
to disable the LDO. Drive with logic signal for logic
control, or program the V
IN
UVLO with a resistor divider between V
IN
, ENL, and A
GND
.
ORDERING INFORMATION
PART NUMBER
SiC401ACD-T1-GE3
SiC401BCD-T1-GE3
SiC401DB
PACKAGE
PowerPAK MLP55-32L
PowerPAK MLP55-32L
Reference board
MARKING (LINE 1: P/N)
SiC401A
SiC401B
Format:
Line 1: P/N
Line 2: Siliconix logo + Lot code + ESD symbol
Line 3: Factory code + Year code + Work week code
S14-2048-Rev. D, 13-Oct-14
Document Number: 63835
3
For technical questions, contact:
powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiC401A, SiC401BCD
www.vishay.com
Vishay Siliconix
CONDITIONS
to P
GND
to V
DD
to P
GND
to P
GND
to P
GND
Reference to A
GND
to P
GND
to LX
to P
GND
LIMITS
-0.3 to +20
-0.4 max.
-0.3 to +20
-2 to +20
-0.3 to +6
-0.3 to +(V
DD
+ 0.3)
-0.3 to +(V
DD
- 1.5)
-0.3 to +6
-0.3 to +25
-0.3 to V
IN
-0.3 to +0.3
150
-65 to 150
IC Section
Ambient Temperature = 25 °C
Ambient Temperature = 100 °C
HBM
CDM
50
3.4
1.3
2
1
V
UNIT
ABSOLUTE MAXIMUM RATINGS
(T
A
= 25 °C, unless otherwise noted)
ELECTRICAL PARAMETER
V
IN
V
IN
LX
LX (Transient < 100 ns)
V
DD
EN/PSV, P
GOOD
, I
LIM
, SS, V
OUT
, FB, FBL
t
ON
BST
ENL
A
GND
to P
GND
Temperature
Maximum Junction Temperature
Storage Temperature
Power Dissipation
Junction to Ambient Thermal Impedance (R
thJA
)
b
Maximum Power Dissipation
ESD Protection
kV
°C/W
W
°C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating/conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(all voltages referenced to GND = 0 V)
PARAMETER
Input Voltage
V
DD
to P
GND
Output Voltage
Temperature
Ambient Temperature
-40 to +85
°C
V
OUT
SYMBOL
V
IN
MIN.
3
3
0.6
TYP.
-
-
-
MAX.
17
5.5
V
IN
x 0.75
V
UNIT
S14-2048-Rev. D, 13-Oct-14
Document Number: 63835
4
For technical questions, contact:
powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiC401A, SiC401BCD
www.vishay.com
Vishay Siliconix
ELECTRICAL SPECIFICATIONS
PARAMETER
Input Power Supplies
Input Supply Voltage
V
DD
V
IN
UVLO Threshold
a
V
IN
UVLO Hysteresis
V
DD
UVLO Threshold
V
DD
UVLO Hysteresis
V
IN
Supply Current
V
IN
V
DD
V
UVLO
V
UVLO, HYS
V
UVLO
V
UVLO, HYS
I
IN
ENL, EN/PSV = 0 V , V
IN
= 17 V
Standby mode; ENL= V
DD
, EN/PSV = 0 V
ENL, EN/PSV = 0 V
SiC401A, EN/PSV = V
DD
, no load
(f
SW
= 25 kHz), V
FB
> 0.6 V
b
V
DD
Supply Current
I
DD
SiC401B, EN/PSV = V
DD
, no load,
V
FB
> 0.6 V
b
V
DD
= 5 V, f
SW
= 250 kHz,
EN/PSV = floating, no load
b
V
DD
= 3 V, f
SW
= 250 kHz,
EN/PSV = floating, no load
b
FB On-Time Threshold
Frequency Range
Bootstrap Switch Resistance
Timing
On-Time
Minimum On-Time
b
Minimum Off-Time
b
Soft Start
Soft Start Current
b
Soft Start Voltage
b
SYMBOL
TEST CONDITIONS UNLESS SPECIFIED
V
IN
= 12 V, V
DD
= 5 V, T
A
= +25 °C for typ.,
-40 °C to +85 °C for min. and max.,
T
J
= < 125 °C, typical application circuit
MIN.
TYP.
MAX.
UNIT
3
3
Sensed at ENL pin, rising
Sensed at ENL pin, falling
Measured at V
DD
pin, rising
Measured at V
DD
pin, falling
2.4
2.23
-
2.5
2.4
-
-
-
-
-
-
-
-
0.594
-
-
-
Continuous mode operation V
IN
= 12 V,
V
OUT
= 5 V, f
SW
= 300 kHz, R
ton
= 133 k
V
DD
= 5 V
V
DD
= 3 V
-
-
2.6
2.4
0.25
-
-
0.2
10
130
190
0.3
0.7
9
5.5
0.600
-
25
10
17
5.5
2.95
2.57
-
3
2.9
-
20
-
300
-
-
mA
-
-
0.606
1000
-
-
V
kHz
μA
V
Static V
IN
and load
f
SW
Continuous mode operation
Minimum f
SW
, (SiC401A only)
t
ON
t
ON, min.
t
OFF, min.
999
-
-
-
-
1110
80
250
370
3
1.5
500
-
± 20
-10
12
7
5
-
10
1220
-
-
-
-
-
-
+3
-
-
-
-
-
1
-
μA
V
k
mV
ns
I
SS
V
SS
R
O-IN
V
Sense-th
PG_V
TH_UPPER
PG_V
TH_LOWER
PG_T
d
PG_I
CC
PG_I
LK
PG_R
DS_ON
LX-P
GND
Upper limit, V
FB
> internal 600 mV reference
Lower limit, V
FB
< internal 600 mV reference
V
DD
= 5 V, C
SS
= 10 nF
V
DD
= 3 V, C
SS
= 10 nF
When V
OUT
reaches regulation
-
-
-3
-
-
-
-
-
-
-
Analog Inputs/Outputs
V
OUT
Input Resistance
Current Sense
Zero-Crossing Detector Threshold Voltage
Power Good
Power Good Threshold
Start-Up Delay Time
(between PWM enable and P
GOOD
high)
Fault (noise-immunity) Delay Time
b
Leakage Current
Power Good On-Resistance
%
ms
μs
μA
S14-2048-Rev. D, 13-Oct-14
Document Number: 63835
5
For technical questions, contact:
powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
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