IRFZ34S, IRFZ34L, SiHFZ34S, SiHFZ34L
www.vishay.com
Vishay Siliconix
Power MOSFET
PRODUCT SUMMARY
V
DS
(V)
R
DS(on)
()
Q
g
(Max.) (nC)
Q
gs
(nC)
Q
gd
(nC)
Configuration
V
GS
= 10 V
46
11
22
Single
D
FEATURES
60
0.050
•
•
•
•
•
•
Advanced process technology
Surface mount
Low-profile through-hole (IRFZ34L, SiHFZ34L)
175 °C operating temperature
Fast switching
Material categorization: for definitions of
compliance
please
see
www.vishay.com/doc?99912
Available
Available
I
2
PAK
(TO-262)
D
2
PAK (TO-263)
Note
*
This datasheet provides information about parts that are
RoHS-compliant and / or parts that are non-RoHS-compliant. For
example, parts with lead (Pb) terminations are not RoHS-compliant.
Please see the information / tables in this datasheet for details.
G
G
D
S
G
D
S
S
N-Channel MOSFET
DESCRIPTION
Third generation power MOSFETs from Vishay utilize
advanced processing techniques to achieve extremely low
on-resistance per silicon area. This benefit, combined with
the fast switching speed and ruggedized device design that
Power MOSFETs are well known for, provides the designer
with an extremely efficient and reliable device for use in a
wide variety of applications.
The D
2
PAK is a surface mount power package capable of
accommodating die sizes up to HEX-4. It provides the
highest power capability and the lowest possible
on-resistance in any existing surface mount package. The
D
2
PAK is suitable for high current applications because of
its low internal connection resistance and can dissipate up
to 2 W in a typical surface mount application.
The through-hole version (IRFZ34L, SiHFZ34L) is available
for low-profile applications.
ORDERING INFORMATION
Package
Lead (Pb)-free and halogen-free
Lead (Pb)-free
Note
a. See device orientation.
D
2
PAK (TO-263)
SiHFZ34S-GE3
IRFZ34SPbF
D
2
PAK (TO-263)
SiHFZ34STRL-GE3
IRFZ34STRLPbF
a
I
2
PAK (TO-262)
SiHFZ34L-GE3
IRFZ34LPbF
ABSOLUTE MAXIMUM RATINGS
(T
C
= 25 °C, unless otherwise noted)
PARAMETER
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
Pulsed Drain
Linear Derating Factor
Single Pulse Avalanche Energy
b, e
Maximum Power Dissipation
Peak Diode Recovery dV/dt
c, e
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak temperature)
d
T
C
= 25 °C
T
A
= 25 °C
Current
a, e
V
GS
at 10 V
T
C
= 25 °C
T
C
= 100 °C
SYMBOL
V
DS
V
GS
I
D
I
DM
E
AS
P
D
dV/dt
T
J
, T
stg
for 10 s
LIMIT
60
± 20
30
21
120
0.59
200
88
3.7
4.5
-55 to +175
300
UNIT
V
A
W/°C
mJ
W
V/ns
°C
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. V
DD
= 25 V, Starting T
J
= 25 °C, L = 260 μH, R
g
= 25
,
I
AS
= 30 A (see fig. 12).
c. I
SD
30 A, dI/dt
200 A/μs, V
DD
V
DS
, T
J
175 °C.
d. 1.6 mm from case.
e. Uses IRFZ34, SiHFZ34 data and test conditions.
S15-1659-Rev. D, 20-Jul-15
Document Number: 90368
1
For technical questions, contact:
hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
IRFZ34S, IRFZ34L, SiHFZ34S, SiHFZ34L
www.vishay.com
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
Maximum Junction-to-Ambient
(PCB mount)
a
Maximum Junction-to-Case (Drain)
SYMBOL
R
thJA
R
thJC
TYP.
-
-
MAX.
40
1.7
UNIT
°C / W
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material).
SPECIFICATIONS
(T
J
= 25 °C, unless otherwise noted)
PARAMETER
Static
Drain-Source Breakdown Voltage
V
DS
Temperature Coefficient
Gate-Source Threshold Voltage
Gate-Source Leakage
Zero Gate Voltage Drain Current
Drain-Source On-State Resistance
Forward Transconductance
Dynamic
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Internal Source Inductance
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
Pulsed Diode Forward
Body Diode Voltage
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
Forward Turn-On Time
Current
a
I
S
I
SM
V
SD
t
rr
Q
rr
t
on
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
DS
V
DS
/T
J
V
GS(th)
I
GSS
I
DSS
R
DS(on)
g
fs
C
iss
C
oss
C
rss
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
L
S
V
GS
= 0 V, I
D
= 250 μA
Reference to 25 °C, I
D
= 1 mA
c
V
DS
= V
GS
, I
D
= 250 μA
V
GS
= ± 20 V
V
DS
= 60 V, V
GS
= 0 V
V
DS
= 48 V, V
GS
= 0 V, T
J
= 150 °C
V
GS
= 10 V
I
D
= 18 A
b
V
DS
= 25 V, I
D
= 18 A
b
60
-
2.0
-
-
-
-
9.3
-
0.065
-
-
-
-
-
-
-
-
4.0
± 100
25
250
0.05
-
V
V/°C
V
nA
μA
S
V
GS
= 0 V,
V
DS
= 25 V,
f = 1.0 MHz, see fig. 5
c
-
-
-
-
1200
600
100
-
-
-
13
100
29
52
7.5
-
-
-
46
11
22
-
-
-
-
-
nH
ns
nC
pF
V
GS
= 10 V
I
D
= 30 A, V
DS
= 48 V,
see fig. 6 and 13
b, c
-
-
-
V
DD
= 30 V, I
D
= 30 A,
R
g
= 12
,
R
D
= 1.0
,
see fig. 10
b, c
-
-
-
Between lead, and center of die contact
-
-
-
-
-
-
-
-
-
120
700
30
A
120
1.6
230
1400
V
ns
μC
G
S
T
J
= 25 °C, I
S
= 30 A, V
GS
= 0 V
b
T
J
= 25 °C, I
F
= 30 A, dI/dt = 100 A/μs
b, c
Intrinsic turn-on time is negligible (turn-on is dominated by L
S
and L
D
)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width
300 μs; duty cycle
2 %.
c. Uses IRFZ34, SiHFZ34 data and test conditions.
S15-1659-Rev. D, 20-Jul-15
Document Number: 90368
2
For technical questions, contact:
hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
IRFZ34S, IRFZ34L, SiHFZ34S, SiHFZ34L
www.vishay.com
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
Vishay Siliconix
Fig. 1 - Typical Output Characteristics
Fig. 3 - Typical Transfer Characteristics
Fig. 2 - Typical Output Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
S15-1659-Rev. D, 20-Jul-15
Document Number: 90368
3
For technical questions, contact:
hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
IRFZ34S, IRFZ34L, SiHFZ34S, SiHFZ34L
www.vishay.com
Vishay Siliconix
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 8 - Maximum Safe Operating Area
S15-1659-Rev. D, 20-Jul-15
Document Number: 90368
4
For technical questions, contact:
hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
IRFZ34S, IRFZ34L, SiHFZ34S, SiHFZ34L
www.vishay.com
Vishay Siliconix
V
DS
V
GS
R
g
R
D
D.U.T.
+
- V
DD
10 V
Pulse width
≤
1 µs
Duty factor
≤
0.1 %
Fig. 10a - Switching Time Test Circuit
V
DS
90 %
10 %
V
GS
t
d(on)
t
r
t
d(off)
t
f
Fig. 9 - Maximum Drain Current vs. Case Temperature
Fig. 10b - Switching Time Waveforms
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
L
Vary t
p
to obtain
required I
AS
R
g
V
DS
t
p
V
DD
D.U.T.
I
AS
10 V
t
p
0.01
W
I
AS
Fig. 12b - Unclamped Inductive Waveforms
V
DS
+
-
V
DD
V
DS
Fig. 12a - Unclamped Inductive Test Circuit
S15-1659-Rev. D, 20-Jul-15
Document Number: 90368
5
For technical questions, contact:
hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
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