STK15C88
32Kx8 PowerStore nvSRAM
FEATURES
• 25, 45 ns Read Access & R/W Cycle Time
• Unlimited Read/Write Endurance
• Pin compatible with industry standard SRAMs
• Automatic Non-volatile STORE on Power Loss
• Automatic RECALL to SRAM on Power Up
• Non-Volatile STORE or RECALL under
Software Control
• Unlimited RECALL Cycles
• 1 Million Store Cycles
• 100-Year Non-volatile Data Retention
• Single 5V +10% Power Supply
• Commercial and Industrial Temperatures
• 28-pin 300-mil and 330 mil SOIC Packages
(RoHS-Compliant)
DESCRIPTION
The Simtek STK15C88 is a 256Kb fast static RAM
with a non-volatile Quantum Trap storage element
included with each memory cell.
The SRAM provides the fast access & cycle times,
ease of use and unlimited read & write endurance of
a normal SRAM.
Data transfers automatically to the non-volatile stor-
age cells when power loss is detected (the
STORE
operation). On power up, data is automatically
restored to the SRAM (the
RECALL
operation). Both
STORE and RECALL operations are also available
under software control.
PowerStore nvSRAM products depend on the intrin-
sic system capacitance to maintain system power
long enough for an automatic store on power loss. If
the power ramp from 5 volts to 3.6 volts is faster
than 10 ms, consider our 14C88 or 16C88 for more
reliable operation.
The Simtek nvSRAM is the first monolithic non-vola-
tile memory to offer unlimited writes and reads. It is
the highest performance, most reliable non-volatile
memory available.
BLOCK DIAGRAM
QUANTUM TRAP
512 x 512
A
5
A
6
A
7
A
8
A
9
A
11
A
12
A
13
A
14
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
STORE/
RECALL
CONTROL
ROW DECODER
STORE
STATIC RAM
ARRAY
512 X 512
RECALL
SOFTWARE
DETECT
A
13
– A
0
INPUT BUFFERS
COLUMN I/O
COLUMN DEC
A
0
A
1
A
2
A
3
A
4
A
10
G
E
W
This product conforms to specifications per the
terms of Simtek standard warranty. The product
has completed Simtek internal qualification testing
and has reached production status.
1
Document Control #ML0016 Rev 2.0
Jan, 2008
STK15C88
PIN CONFIGURATIONS
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
(TOP)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
W
A
13
A
8
A
9
A
11
G
A
10
E
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
28 Pin 300 mil SOIC
28 Pin 330 mil SOIC
PIN DESCRIPTIONS
Pin Name
A
14
-A
0
DQ
7
-DQ
0
E
W
G
V
CC
V
SS
Input
I/O
Input
Input
Input
Power Supply
Power Supply
I/O
Description
Address: The 15 address inputs select one of 32,768 bytes in the nvSRAM array
Data: Bi-directional 8-bit data bus for accessing the nvSRAM
Chip Enable: The active low E input selects the device
Write Enable: The active low W enables data on the DQ pins to be written to the address
location latched by the falling edge of E
Output Enable: The active low G input enables the data output buffers during read cycles.
De-asserting G high caused the DQ pins to tri-state.
Power: 5.0V, +10%
Ground
Document Control #ML0016 Rev 2.0
Jan, 2008
2
STK15C88
ABSOLUTE MAXIMUM RATINGS
a
Voltage on Input Relative to Ground . . . . . . . . . . . . . –0.5V to 7.0V
Voltage on Input Relative to V
SS
. . . . . . . . . . –0.6V to (V
CC
+ 0.5V)
Voltage on DQ
0-7
. . . . . . . . . . . . . . . . . . . . . . –0.5V to (V
CC
+ 0.5V)
Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration) . . . . . . . . 15mA
Note a: Stresses greater than those listed under “Absolute Maximum Rat-
ings” may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at conditions
above those indicated in the operational sections of this specifica-
tion is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect reliability.
DC CHARACTERISTICS
COMMERCIAL
SYMBOL
I
CC1
b
I
CC2
c
I
CC3
b
I
CC4
c
I
SB1
d
I
SB2
d
I
ILK
I
OLK
V
IH
V
IL
V
OH
V
OL
T
A
PARAMETER
MIN
Average V
CC
Current
Average V
CC
Current during
STORE
Average V
CC
Current at t
AVAV
= 200ns
5V, 25°C, Typical
Average V
CAP
Current during
AutoStore Cycle
Average V
CC
Current
(Standby, Cycling TTL Input Levels)
V
CC
Standby Current
(Standby, Stable CMOS Input Levels)
Input Leakage Current
Off-State Output Leakage Current
Input Logic “1” Voltage
Input Logic “0” Voltage
Output Logic “1” Voltage
Output Logic “0” Voltage
Operating Temperature
0
2.2
V
SS
– .5
2.4
0.4
70
– 40
MAX
97
70
3
10
2
30
22
1.5
±1
±5
V
CC
+ .5
0.8
2.2
V
SS
– .5
2.4
0.4
85
MIN
MAX
100
70
3
10
2
31
23
1.5
±1
±5
V
CC
+ .5
0.8
mA
mA
mA
mA
mA
mA
mA
mA
μA
μA
V
V
V
V
°C
INDUSTRIAL
UNITS
(V
CC
= 5.0V
±
10%)
NOTES
t
AVAV
= 25ns
t
AVAV
= 45ns
All Inputs Don’t Care, V
CC
= max
W
≥
(V
CC
– 0.2V)
All Others Cycling, CMOS Levels
All Inputs Don’t Care
t
AVAV
= 25ns, E
≥
V
IH
t
AVAV
= 45ns, E
≥
V
IH
E
≥
(V
CC
– 0.2V)
All Others V
IN
≤
0.2V or
≥
(V
CC
– 0.2V)
V
CC
= max
V
IN
= V
SS
to V
CC
V
CC
= max
V
IN
= V
SS
to V
CC
, E or G
≥
V
IH
All Inputs
All Inputs
I
OUT
= – 4mA
I
OUT
= 8mA
Note b: I
CC1
and I
CC3
are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
Note c: I
CC2
and I
CC4
are the average currents required for the duration of the respective
STORE
cycles (t
STORE
) .
Note d: E
≥
V
IH
will not produce standby current levels until any nonvolatile cycle in progress has timed out.
AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V
Input Rise and Fall Times
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤
5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
5.0V
CAPACITANCE
e
SYMBOL
C
IN
C
OUT
PARAMETER
Input Capacitance
Output Capacitance
(T
A
= 25
°
C, f = 1.0MHz)
MAX
5
7
UNITS
pF
pF
CONDITIONS
480 Ohms
OUTPUT
255 Ohms
ΔV
= 0 to 3V
ΔV
= 0 to 3V
Note e: These parameters are guaranteed but not tested.
30 pF
INCLUDING
SCOPE AND
FIXTURE
Figure 1: AC Output Loading
Document Control #ML0016 Rev 2.0
Jan, 2008
3
STK15C88
SRAM READ CYCLES #1 & #2
SYMBOLS
NO.
1
2
3
4
5
6
7
8
9
10
11
PARAMETER
#1, #2
t
ELQV
t
AVAV
t
ELEH
t
AVQV
g
f
,
f
(V
CC
= 5.0V
±
10%)
STK15C88-25
STK15C88-45
UNITS
MIN
MAX
25
25
25
10
5
5
10
0
10
0
25
0
45
0
15
5
5
15
45
45
20
MIN
MAX
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Alt.
t
ACS
t
RC
t
AA
t
OE
t
OH
t
LZ
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold after Address Change
Address Change or Chip Enable to Output Active
Address Change or Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
t
GLQV
t
AXQX
g
t
ELQX
t
EHQZ
t
GLQX
t
GHQZ
h
e
d
,
e
h
t
HZ
t
OLZ
t
OHZ
t
PA
t
PS
t
ELICCH
t
EHICCL
Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles.
Note g: I/O state assumes E, G < V
IL
and W > V
IH
; device is continuously selected.
Note h: Measured + 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlled
f, g
2
t
AVAV
ADDRESS
5
t
AXQX
DQ (DATA OUT)
DATA VALID
3
t
AVQV
SRAM READ CYCLE #2: E and G Controlled
f
ADDR ESS
t
E LE H
1
t
EL Q V
2
29
t
EHAX
11
t
EHI CC L
7
t
EHQ Z
E
27
6
t
ELQ X
G
t
AV QV
4
t
G L QV
9
t
GH Q Z
3
8
t
G L Q X
DQ (D ATA OUT)
10
t
ELI CC H
DAT A VAL ID
AC T IVE
I
CC
ST AND BY
Document Control #ML0016 Rev 2.0
Jan, 2008
4
STK15C88
SRAM WRITE CYCLES #1 & #2
SYMBOLS
NO.
#1
#2
Alt.
PARAMETER
MIN
MAX
MIN
MAX
(V
CC
= 5.0V
±
10%)
STK15C88-25
STK15C88-45
UNITS
12
13
14
15
16
17
18
19
20
21
t
AVAV
t
WLWH
t
ELWH
t
DVWH
t
WHDX
t
AVWH
t
AVWL
t
WHAX
t
WLQZ
h, i
t
WHQX
t
AVAV
t
WLEH
t
ELEH
t
DVEH
t
EHDX
t
AVEH
t
AVEL
t
EHAX
t
WC
t
WP
t
CW
t
DW
t
DH
t
AW
t
AS
t
WR
t
WZ
t
OW
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
25
20
20
10
0
20
0
0
10
5
45
30
30
15
0
30
0
0
15
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note i:
Note j:
If W is low when E goes low, the outputs remain in the high-impedance state.
E or W must be
≥
V
IH
during address transitions.
SRAM WRITE CYCLE #1: W Controlled
j
12
t
AVAV
ADDRESS
14
t
ELWH
E
17
t
AVWH
13
t
WLWH
15
t
DVWH
DATA IN
20
t
WLQZ
PREVIOUS DATA
DATA VALID
19
t
WHAX
18
t
AVWL
W
16
t
WHDX
DATA OUT
HIGH IMPEDANCE
21
t
WHQX
SRAM WRITE CYCLE #2:
E Controlled
j
12
t
AVAV
ADDRESS
18
t
AVEL
E
14
t
ELEH
19
t
EHAX
17
t
AVEH
W
13
t
WLEH
15
t
DVEH
16
t
EHDX
DATA VALID
HIGH IMPEDANCE
DATA IN
DATA OUT
Document Control #ML0016 Rev 2.0
Jan, 2008
5
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