STK16CA8
128K x 8
AutoStorePlus™
nvSRAM
QuantumTrap™
CMOS
Nonvolatile Static RAM
Preliminary
FEATURES
• 25ns, 35ns and 45ns Access Times
• Directly Replaces 128K x 8 Static RAM, Bat-
tery-Backed RAM or EEPROM
• Transparent Data Save on Power Down
•
STORE
to
QuantumTrap™
Nonvolatile Ele-
ments is Initiated by Software or
AutoStore-
Plus™on
Power Down
•
RECALL
to SRAM Initiated by Software or
Power Restore
• 5mA Typical I
CC
at 200ns Cycle Time
• Unlimited READ and WRITE Cycles to SRAM
• 100-Year Data Retention to Quantum Trap
• Single 3V +20%, -10% Operation
• Commercial and Industrial Temperatures
• 32-Pin DIP Package
DESCRIPTION
The Simtek STK16CA8 is a fast static
RAM
with a
nonvolatile element in each static memory cell. The
embedded nonvolatile elements incorporate
Simtek’s
QuantumTrap™
technology producing the
world’s most reliable nonvolatile memory. The
SRAM
provides unlimited read and write cycles, while inde-
pendent, nonvolatile data resides in the nonvolatile
elements. Data transfers from the
SRAM
to the non-
volatile elements (the
STORE
operation) can take
place automatically on power down or under soft-
ware control. An internal capacitor guarantees the
STORE
operation, even under extreme power-down
slew rates or loss of power from “hot swapping”.
Transfers from the nonvolatile elements to the
SRAM
(the
RECALL
operation) take place automatically on
restoration of power. Initiation of
STORE
and
RECALL
cycles can also be controlled by entering control
sequences on the
SRAM
inputs. The STK16CA8 is
pin-compatible with 128k x 8
SRAMs
and battery-
backed
SRAMs
, allowing direct substitution while
providing superior performance.
BLOCK DIAGRAM
V
CC
Quantum Trap
1024 x 1024
ROW DECODER
PIN CONFIGURATIONS
NC
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A
5
A
6
A
7
A
8
A
9
A
12
A
13
A
14
A
15
A
16
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
POWER
CONTROL
STORE
STATIC RAM
ARRAY
1024 x 1024
RECALL
STORE/
RECALL
CONTROL
V
CC
A
15
NC
W
A
13
A
8
A
9
A
11
G
A
10
E
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
INPUT BUFFERS
COLUMN I/O
COLUMN DEC
SOFTWARE
DETECT
A
0
- A
15
PIN NAMES
A
0
- A
16
W
DQ
0
- DQ
7
Address Inputs
Write Enable
Data In/Out
Chip Enable
Output Enable
Power (+ 3V)
Ground
A
0
A
1
A
2
A
3
A
4
A
10
A
11
G
E
W
E
G
V
CC
V
SS
September 2003
1
Document Control # ML0023 rev 0.1
STK16CA8
ABSOLUTE MAXIMUM RATINGS
a
Power Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . –0.5V to +3.9V
Voltage on Input Relative to V
SS
. . . . . . . . . .–0.5V to (V
CC
+ 0.5V)
Voltage on DQ
0-7
. . . . . . . . . . . . . . . . . . . . . .–0.5V to (V
CC
+ 0.5V)
Temperature under Bias. . . . . . . . . . . . . . . . . . . . . .–55°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .–65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration) . . . . . . . 15mA
Note a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at con-
ditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
DC CHARACTERISTICS
SYMBOL
I
CC b
1
(V
CC
= 3.0V
+20%,
-10%)
COMMERCIAL
MIN
MAX
50
40
35
1.5
5
1
±1
±1
2.0
V
SS
– .5
2.4
0.4
0
70
– 40
V
CC
+ .3
0.8
2.0
V
SS
– .5
2.4
0.4
85
INDUSTRIAL
MIN
MAX
55
45
35
1.5
5
1
±1
±1
V
CC
+ .3
0.8
UNITS
mA
mA
mA
mA
mA
mA
µA
µA
V
V
V
V
°C
t
AVAV
= 25ns
t
AVAV
= 35ns
t
AVAV
= 45ns
All Inputs Don’t Care, V
CC
= max
W
≥
(V
CC
– 0.2V)
All Others Cycling, CMOS Levels
E
≥
(V
CC
– 0.2V)
All Others V
IN
≤
0.2V or
≥
(V
CC
– 0.2V)
V
CC
= max
V
IN
= V
SS
to V
CC
V
CC
= max
V
IN
= V
SS
to V
CC
, E or G
≥
V
IH
All Inputs
All Inputs
I
OUT
= – 2mA
I
OUT
= 4mA
NOTES
PARAMETER
Average V
CC
Current
I
CC c
2
3
Average V
CC
Current during
STORE
Average V
CC
Current at t
AVAV
= 200ns
3V, 25°C, Typical
V
CC
Standby Current
(Standby, Stable CMOS Input Levels)
Input Leakage Current
Off-State Output Leakage Current
Input Logic “1” Voltage
Input Logic “0” Voltage
Output Logic “1” Voltage
Output Logic “0” Voltage
Operating Temperature
I
CC
b
I
SBd
I
ILK
I
OLK
V
IH
V
IL
V
OH
V
OL
T
A
Note b: I
CC
and I
CC
are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
1
3
Note c: I
CC
is the average current required for the duration of the
STORE
cycle (t
STORE
) .
2
Note d: E
≥
V
IH
will not produce standby current levels until any nonvolatile cycle in progress has timed out.
AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V
Input Rise and Fall Times.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤
5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
CAPACITANCE
e
SYMBOL
C
IN
C
OUT
PARAMETER
Input Capacitance
Output Capacitance
(T
A
= 25°C, f = 1.0MHz)
MAX
5
7
UNITS
pF
pF
CONDITIONS
∆V
= 0 to 3V
∆V
= 0 to 3V
3.0V
577 Ohms
OUTPUT
789 Ohms
30 pF
INCLUDING
SCOPE AND
FIXTURE
Note e: These parameters are guaranteed but not tested.
Figure 1
:
AC Output Loading
September 2003
2
Document Control # ML0023 rev 0.1
STK16CA8
SRAM READ CYCLES #1 & #2
NO.
1
2
3
4
5
6
7
8
9
10
11
SYMBOLS
#1, #2
t
ELQV
t
AVAVf
t
AVQVg
t
GLQV
t
AXQXg
t
ELQX
t
EHQZ
h
(V
CC
= 3.0V +20%, -10%)
PARAMETER
STK16CA8-25
MIN
MAX
25
25
25
10
3
3
10
0
10
0
25
0
35
0
13
0
45
3
3
13
0
15
35
35
15
3
3
15
STK16CA8-35
MIN
MAX
35
45
45
20
STK16CA8-45
MIN
MAX
45
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Alt.
t
ACS
t
RC
t
AA
t
OE
t
OH
t
LZ
t
HZ
t
OLZ
t
OHZ
e
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
t
GLQX
t
GHQZh
t
ELICCH
t
EHICCLe
t
PA
t
PS
Note f: W must be high during SRAM READ cycles.
Note g: Device is continuously selected with E and G both low.
Note h: Measured
±
200mV from steady state output voltage.
SRAM READ CYCLE #1:
Address Controlled
f, g
2
t
AVAV
ADDRESS
5
3
t
AVQV
DATA VALID
t
AXQX
DQ (DATA OUT)
SRAM READ CYCLE #2:
E Controlled
f
2
t
AVAV
ADDRESS
6
1
t
ELQV
1
1
t
EHICCL
7
t
EHQZ
E
t
ELQX
G
8
t
GLQX
DQ (DATA OUT)
t
ELICCH
ACTIVE
t
GLQV
4
9
t
GHQZ
DATA VALID
10
I
CC
STANDBY
September 2003
3
Document Control # ML0023 rev 0.1
STK16CA8
SRAM WRITE CYCLES #1 & #2
NO.
12
13
14
15
16
17
18
19
20
21
SYMBOLS
#1
t
AVAV
t
WLWH
t
ELWH
t
DVWH
t
WHDX
t
AVWH
t
AVWL
t
WHAX
t
WLQZ h, i
t
WHQX
#2
t
AVAV
t
WLEH
t
ELEH
t
DVEH
t
EHDX
t
AVEH
t
AVEL
t
EHAX
Alt.
t
WC
t
WP
t
CW
t
DW
t
DH
t
AW
t
AS
t
WR
t
WZ
t
OW
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
3
PARAMETER
MIN
25
20
20
10
0
20
0
0
10
3
(V
CC
= 3.0V
+20%,
-10%)
STK16CA8-25
MAX
STK16CA8-35
MIN
35
25
25
12
0
25
0
0
13
3
MAX
STK16CA8-45
MIN
45
30
30
15
0
30
0
0
15
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note i:
Note j:
If W is low when E goes low, the outputs remain in the high-impedance state.
E or W must be
≥
V
IH
during address transitions.
SRAM WRITE CYCLE #1:
W Controlled
j
12
t
AVAV
ADDRESS
t
ELWH
E
17
t
AVWH
13
t
WLWH
15
t
DVWH
DATA IN
t
WLQZ
DATA OUT
PREVIOUS DATA
HIGH IMPEDANCE
DATA VALID
14
19
t
WHAX
18
t
AVWL
W
16
t
WHDX
20
21
t
WHQX
SRAM WRITE CYCLE #2:
E Controlled
j
12
t
AVAV
ADDRESS
18
t
AVEL
E
14
t
ELEH
19
t
EHAX
17
t
AVEH
W
13
t
WLEH
15
t
DVEH
16
t
EHDX
DATA VALID
HIGH IMPEDANCE
DATA IN
DATA OUT
September 2003
4
Document Control # ML0023 rev 0.1
STK16CA8
MODE SELECTION
E
H
L
L
W
X
H
L
G
X
L
X
A
15
- A
0
(hex)
X
X
X
4E38
B1C7
83E0
7C1F
703F
8B45
4E38
B1C7
83E0
7C1F
703F
4B46
4E38
B1C7
83E0
7C1F
703F
8FC0
4E38
B1C7
83E0
7C1F
703F
4C63
MODE
Not Selected
Read SRAM
Write SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Autostore Inhibit
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Autostore inhibit off
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Store
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Recall
I/O
Output High Z
Output Data
Input Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
POWER
Standby
Active
Active
NOTES
L
H
L
Active
k, l, m
L
H
L
Active
k, l, m
L
H
L
Active
k, l, m
l
CC
2
L
H
L
Active
k, l, m
Note k: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.
Note l: While there are 17 addresses on the STK16CA8, only the lower 16 are used to control software modes.
Note m: I/O state depends on the state of G. The I/O table shown assumes G low.
September 2003
5
Document Control # ML0023 rev 0.1
Power technology
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