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STK22C48N45

Description
2K x 8 AutoStore™ nvSRAM QuantumTrap™ CMOS Nonvolatile Static RAM
File Size193KB,11 Pages
ManufacturerETC1
Download Datasheet View All

STK22C48N45 Overview

2K x 8 AutoStore™ nvSRAM QuantumTrap™ CMOS Nonvolatile Static RAM

STK22C48
2K x 8
AutoStore™
nvSRAM
QuantumTrap™
CMOS
Nonvolatile Static RAM
FEATURES
• 25ns, 35ns and 45ns Access Times
• “Hands-off” Automatic
STORE
with External
68µF Capacitor on Power Down
STORE
to Nonvolatile Elements Initiated by
Hardware or
AutoStore™
on Power Down
• Automatic
RECALL
on Power Up
• 10mA Typical I
CC
at 200ns Cycle Time
• Unlimited READ, WRITE and
RECALL
Cycles
• 1,000,000
STORE
Cycles to Nonvolatile Ele-
ments
• 100-Year Data Retention in Nonvolatile Ele-
ments
• Single 5V + 10% Operation
• Commercial and Industrial Temperatures
• 28-Pin DIP and SOIC Packages
DESCRIPTION
The Simtek STK22C48 is a fast static
RAM
with a
nonvolatile element incorporated in each static
memory cell. The
SRAM
can be read and written an
unlimited number of times, while independent, non-
volatile data resides in Nonvolatile Elements. Data
transfers from the
SRAM
to the Nonvolatile Elements
(the
STORE
operation) can take place automatically
on power down. A 68µF or larger capacitor tied from
V
CAP
to ground guarantees the
STORE
operation,
regardless of power-down slew rate or loss of power
from “hot swapping”. Transfers from the Nonvolatile
Elements to the
SRAM
(the
RECALL
operation) take
place automatically on restoration of power. A hard-
ware
STORE
may be initiated with the HSB pin.
BLOCK DIAGRAM
V
CCX
V
CAP
POWER
CONTROL
PIN CONFIGURATIONS
V
CAP
NC
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Quantum Trap
32 x 512
ROW DECODER
A
5
A
6
A
7
A
8
A
9
STORE
STATIC RAM
ARRAY
32 x 512
RECALL
STORE/
RECALL
CONTROL
HSB
V
CCX
W
HSB
A
8
A
9
NC
G
A
10
E
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
28 - 300 PDIP
28 - 600 PDIP
28 - 300 SOIC
28 - 350 SOIC
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
INPUT BUFFERS
COLUMN I/O
COLUMN DEC
PIN NAMES
A
0
- A
10
DQ
0
-DQ
7
E
W
Address Inputs
Data In/Out
Chip Enable
Write Enable
Output Enable
Hardware Store Busy (I/O)
Power (+ 5V)
Capacitor
Ground
A
0
A
1
A
2
A
3
A
4
A
10
G
E
W
G
HSB
V
CCX
V
CAP
V
SS
December 2002
1
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