STM6780LTGWB6E datasheet, PDF - EEWORLD Datasheet

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STM6780LTGWB6E: DescriptionDual/triple ultra-low voltage supervisors with push-button reset (with delay option); File Size195KB，29 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/

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STM6780LTGWB6E Overview

Dual/triple ultra-low voltage supervisors with push-button reset (with delay option)

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STM6717/6718/6719/6720

STM6777/6778/6779/6780

Dual/triple ultra-low voltage supervisors

with push-button reset (with delay option)

Features

■

Primary supply (V

CC1

) monitor. Fixed (factory-

programmed) reset thresholds: 4.63V to 1.58V

Secondary supply (V

CC2

) monitor

(STM6717/18/19/20/77/78).

Fixed (factory-programmed) reset thresholds:

3.08V to 0.79V

Tertiary supply monitor (using externally

adjustable rstin):

0.626V internal reference

RST outputs (push-pull or open drain); state

guaranteed IF V

CC1

OR V

CC2

≥

0.8V

Reset delay time (t

rec

) on power-up: 210ms,

900ms (typ)

Manual reset input (MR)

Optional delayed manual reset input (MRC)

with external capacitor (STM6777/78/79/80)

Low supply current - 11µA (typ),

CC1

= V

CC2

= 3.6V

Operating temperature: –40°C to 85°C

(industrial grade)

Device summary

Monitored voltages

Part

number

STM6717

STM6718

STM6719

STM6720

STM6777

STM6778

STM6779

STM6780

CC1

✔

CC2

✔

RSTIN

Manual reset

input (MR)

✔

Delayed

MR pin

(MRC)

Reset output (RST)

Active-low

(push-pull)

Active-low

(open drain)

✔

Package

SOT23-6 (WB)

SOT23-5 (WY)

Table 1.

December 2007

Rev 6

1/29

www.st.com

List of figures

STM6717/6718/6719/6720/STM6777/6778/6779/6780

List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

Figure 10.

Figure 11.

Figure 12.

Figure 13.

Figure 14.

Figure 15.

Figure 16.

Figure 17.

Figure 18.

Figure 19.

Figure 20.

Figure 21.

Figure 22.

Figure 23.

Figure 24.

Figure 25.

Figure 26.

Figure 27.

Figure 28.

Figure 29.

Logic diagram (STM6717/18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Logic diagram (STM6777/78) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Logic diagram (STM6719/20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Logic diagram (STM6779/80) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

STM6717/18 SOT23-5 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

STM6777/78 SOT23-6 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

STM6719/20 SOT23-6 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

STM6779/80 SOT23-6 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

STM67xx interface to processor with bi-directional reset pins . . . . . . . . . . . . . . . . . . . . . . 10

Ensuring RST valid to V

= 0 (active-low, push-pull outputs). . . . . . . . . . . . . . . . . . . . . . 10

Supply current vs. temperature (V

CC1

= 5.5V; V

CC2

= 3.6V) . . . . . . . . . . . . . . . . . . . . . . . 11

Supply current vs. temperature (V

CC1

= 3.6V; V

CC2

= 2.75V) . . . . . . . . . . . . . . . . . . . . . . 11

Supply current vs. temperature (V

CC1

= 3.0V; V

CC2

= 2.0V) . . . . . . . . . . . . . . . . . . . . . . . 12

Supply current vs. temperature (V

CC1

= 2.0V; V

CC2

= 1.0V) . . . . . . . . . . . . . . . . . . . . . . . 12

Normalized V

reset time-out period vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Maximum V

transient duration vs. reset threshold overdrive . . . . . . . . . . . . . . . . . . . . . 13

Normalized V

RST1

threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Normalized V

RST2

threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Reset input threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

CC1

-to-reset delay vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Reset input-to-reset output delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

MR-to-reset output delay vs. temperature (V

CC1

= 3.6V) . . . . . . . . . . . . . . . . . . . . . . . . . . 16

AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

MR timing waveform (STM6717/18/19/20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

MR timing waveform (STM6777/78/79/80) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

SOT23-5 – 5-lead small outline transistor package mechanical drawing . . . . . . . . . . . . . . 22

SOT23-6 – 6-lead small outline transistor package mechanical drawing . . . . . . . . . . . . . . 23

4/29

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