STM8S105C6T3CTR datasheet, PDF

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STM8S105C6T3CTR: Description8-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP48; CategoryThe embedded processor and controller Microcontrollers and processors; File Size2MB，121 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/

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STM8S105C6T3CTR Overview

8-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP48

STM8S105C6T3CTR Parametric

Parameter Name	Attribute value
Maker	STMicroelectronics
Reach Compliance Code	compli
Has ADC	YES
Address bus width
bit size	8
maximum clock frequency	16 MHz
DMA channel	NO
External data bus width
length	7 mm
Number of I/O lines	38
Number of terminals	48
PWM channel	YES
encapsulated code	LFQFP
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
speed	16 MHz
Maximum supply voltage	5.5 V
Minimum supply voltage	2.95 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
width	7 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER

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STM8S105C4/6 STM8S105K4/6

STM8S105S4/6

Access line, 16 MHz STM8S 8-bit MCU, up to 32 Kbyte Flash,

integrated EEPROM, 10-bit ADC, timers, UART, SPI, I²C

Datasheet

production data

Features

Core



16 MHz advanced STM8 core with Harvard

architecture and 3-stage pipeline



Extended instruction set

LQFP48 (7x7 mm)

LQFP44 (10x10 mm)

LQFP32 (7x7 mm)

Memories



Program memory: up to 32 Kbyte Flash; data

retention 20 years at 55 °C after 10 kcycle



Data memory: up to 1 Kbyte true data

EEPROM; endurance 300 kcycle



RAM: up to 2 Kbyte

UFQFPN32 (5x5 mm)

SDIP32 400ml



2x16-bit general purpose timer, with 2+3

CAPCOM channels (IC, OC or PWM)



8-bit basic timer with 8-bit prescaler



Auto wake-up timer



Window watchdog and independent watchdog

timers

Clock, reset and supply management



2.95 to 5.5 V operating voltage



Flexible clock control, 4 master clock sources

– Low power crystal resonator oscillator

– External clock input

– Internal, user-trimmable 16 MHz RC

– Internal low-power 128 kHz RC



Clock security system with clock monitor



Power management:

– Low-power modes (wait, active-halt, halt)

– Switch-off peripheral clocks individually



Permanently active, low-consumption power-

on and power-down reset

Communication interfaces



UART with clock output for synchronous

operation, SmartCard, IrDA, LIN master mode



SPI interface up to 8 Mbit/s



I2C interface up to 400 kbit/s

Analog to digital converter (ADC)



10-bit, ±1 LSB ADC with up to 10 multiplexed

channels, scan mode and analog watchdog

Interrupt management



Nested interrupt controller with 32 interrupts



Up to 37 external interrupts on 6 vectors

I/Os



Up to 38 I/Os on a 48-pin package including



16 high sink outputs



Highly robust I/O design, immune against

current injection

Timers



Advanced control timer: 16-bit, 4 CAPCOM

channels, 3 complementary outputs, dead-time

insertion and flexible synchronization

Unique ID



96-bit unique key for each device

September 2015

This is information on a product in full production.

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www.st.com

Contents

STM8S105x4/6

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

4.10

4.11

4.12

4.13

4.14

Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Single wire interface module (SWIM) and debug module (DM) . . . . . . . . 14

Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Flash program and data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . 14

Clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Auto wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

TIM1 - 16-bit advanced control timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

TIM2, TIM3 - 16-bit general purpose timers . . . . . . . . . . . . . . . . . . . . . . . 18

TIM4 - 8-bit basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Analog-to-digital converter (ADC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.14.1

4.14.2

4.14.3

UART2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.1

Alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.1

6.2

Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.2.1

6.2.2

I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

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STM8S105x4/6

6.2.3

Contents

CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . 42

Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Option byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

8.1

Alternate function remapping bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Unique ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

10.1

Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

10.1.1

10.1.2

10.1.3

10.1.4

10.1.5

10.1.6

Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Typical current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

10.2

10.3

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

10.3.1

10.3.2

10.3.3

10.3.4

10.3.5

10.3.6

10.3.7

10.3.8

10.3.9

VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

External clock sources and timing characteristics . . . . . . . . . . . . . . . . . 66

Internal clock sources and timing characteristics . . . . . . . . . . . . . . . . . 69

Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Typical output level curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

SPI serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

10.3.10 I

C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

10.3.11 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

10.3.12 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

11.1

11.2

11.3

11.4

LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

LQFP44 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

UFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

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STM8S105x4/6

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Table 16.

Table 17.

Table 18.

Table 19.

Table 20.

Table 21.

Table 22.

Table 23.

Table 24.

Table 25.

Table 26.

Table 27.

Table 28.

Table 29.

Table 30.

Table 31.

Table 32.

Table 33.

Table 34.

Table 35.

Table 36.

Table 37.

Table 38.

Table 39.

Table 40.

Table 41.

Table 42.

Table 43.

Table 44.

Table 45.

Table 46.

Table 47.

Table 48.

STM8S105x4/6 access line features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers . . . . . . . . . . . . . . . 16

TIM timer features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Legend/abbreviations for pin description tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

STM8S105x4/6 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Flash, data EEPROM and RAM boundary address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Option byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Alternate function remapping bits [7:0] of OPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Unique ID registers (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Total current consumption with code execution in run mode at V

= 5 V. . . . . . . . . . . . . 57

Total current consumption with code execution in run mode at V

= 3.3 V . . . . . . . . . . . 58

Total current consumption in wait mode at V

= 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Total current consumption in wait mode at V

= 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Total current consumption in active halt mode at V

= 5 V . . . . . . . . . . . . . . . . . . . . . . . 59

Total current consumption in active halt mode at V

= 3.3 V . . . . . . . . . . . . . . . . . . . . . . 60

Total current consumption in halt mode at V

= 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Total current consumption in halt mode at V

= 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Wakeup times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Total current consumption and timing in forced reset state . . . . . . . . . . . . . . . . . . . . . . . . 61

Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

HSE user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Flash program memory/data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Output driving current (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

ADC accuracy with R

AIN

< 10 k, V

DDA

= 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

ADC accuracy with R

AIN

< 10 k, V

DDA

= 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

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