MT48LC4M32B2F51 datasheet, PDF

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MT48LC4M32B2F51: Description4M X 32 SYNCHRONOUS DRAM, 5.5 ns, PDSO86; Categorystorage; File Size4MB，80 Pages; ManufacturerMicron; Websitehttp://www.micron.com/

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MT48LC4M32B2F51 Overview

4M X 32 SYNCHRONOUS DRAM, 5.5 ns, PDSO86

MT48LC4M32B2F51 Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	86
Maximum operating temperature	70 Cel
Minimum operating temperature	0.0 Cel
Maximum supply/operating voltage	3.6 V
Minimum supply/operating voltage	3 V
Rated supply voltage	3.3 V
Minimum access time	5.5 ns
Processing package description	0.40 INCH, Lead FREE, Plastic, TSOP-86
Lead-free	Yes
EU RoHS regulations	Yes
China RoHS regulations	Yes
state	EOL/LIFEBUY
Craftsmanship	CMOS
packaging shape	Rectangle
Package Size	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
surface mount	Yes
Terminal form	GULL WING
Terminal spacing	0.5000 mm
terminal coating	MATTE Tin
Terminal location	pair
Packaging Materials	Plastic/Epoxy
Temperature level	COMMERCIAL
memory width	32
organize	4M × 32
storage density	1.34E8 deg
operating mode	Synchronize
Number of digits	4.19E6 words
Number of digits	4M
Access method	Four BANK PAGE BURST
Memory IC type	synchronous dynamic random access memory
Number of ports	1

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128Mb: x32 SDRAM

Features

SDR SDRAM

MT48LC4M32B2 – 1 Meg x 32 x 4 Banks

Features

• PC100-compliant

• Fully synchronous; all signals registered on positive

edge of system clock

• Internal pipelined operation; column address can

be changed every clock cycle

• Internal banks for hiding row access/precharge

• Programmable burst lengths: 1, 2, 4, 8, or full page

• Auto precharge, includes concurrent auto precharge

and auto refresh modes

• Self refresh mode (not available on AT devices)

• Auto refresh

– 64ms, 4096-cycle refresh (15.6µs/row; commer-

cial and industrial)

– 16ms, 4096-cycle refresh (3.9µs/row; automotive)

• LVTTL-compatible inputs and outputs

• Single 3.3V ±0.3V power supply

• Supports CAS latency (CL) of 1, 2, and 3

Table 1: Address Table

Parameter

Configuration

Refresh count

Row addressing

Bank addressing

Column addressing

4 Meg x 32

1 Meg x 32 x 4 banks

4K A[11:0]

4 BA[1:0]

256 A[7:0]

Options

• Configuration

– 4 Meg x 32 (1 Meg x 32 x 4 banks)

• Package – OCPL

– 86-pin TSOP II (400 mil)

– 86-pin TSOP II (400 mil) Pb-free

– 90-ball VFBGA (8mm x 13mm)

– 90-ball VFBGA (8mm x 13mm) Pb-

free

• Timing (cycle time)

– 6ns (166 MHz)

– 7ns (143 MHz)

• Revision

• Operating temperature range

– Commercial (0°C to +70°C)

– Industrial (–40°C to +85°C)

– Automotive (–40°C to +105°C)

Notes:

1. Off-center parting line.

2. Available on -6 and -7.

3. Contact Micron for availability.

Marking

4M32B2

-6

-7

:G, :L

None

Table 3: 128Mb (x32) SDR Part Numbering

Part Numbers

MT48LC4M32B2TG

MT48LC4M32B2P

MT48LC4M32B2F5

MT48LC4M32B2B5

Note:

Architecture

4 Meg x 32

Table 2: Key Timing Parameters

CL = CAS (READ) latency

Speed

Grade

-6

-7

Clock

Frequency

166 MHz

143 MHz

Access

Time

CL = 3

5.5ns

Setup

Time

1.5ns

2ns

Hold

Time

1ns

1. FBGA Device Decoder:

www.micron.com/

decoder.

PDF: 09005aef80872800

128mb_x32_sdram.pdf - Rev. P 9/11 EN

Products and specifications discussed herein are subject to change by Micron without notice.

Micron Technology, Inc. reserves the right to change products or specifications without notice.

128Mb: x32 SDRAM

Features

Contents

General Description ......................................................................................................................................... 6

Automotive Temperature .............................................................................................................................. 6

Functional Block Diagram ................................................................................................................................ 7

Pin and Ball Assignments and Descriptions ....................................................................................................... 8

Package Dimensions ....................................................................................................................................... 11

Temperature and Thermal Impedance ............................................................................................................ 14

Electrical Specifications .................................................................................................................................. 17

Electrical Specifications – I

Parameters ........................................................................................................ 18

Electrical Specifications – AC Operating Conditions ......................................................................................... 20

Functional Description ................................................................................................................................... 23

Commands .................................................................................................................................................... 24

COMMAND INHIBIT .................................................................................................................................. 24

NO OPERATION (NOP) ............................................................................................................................... 25

LOAD MODE REGISTER (LMR) ................................................................................................................... 25

ACTIVE ...................................................................................................................................................... 25

READ ......................................................................................................................................................... 26

WRITE ....................................................................................................................................................... 27

PRECHARGE .............................................................................................................................................. 28

BURST TERMINATE ................................................................................................................................... 28

AUTO REFRESH ......................................................................................................................................... 29

SELF REFRESH ........................................................................................................................................... 29

Truth Tables ................................................................................................................................................... 30

Initialization .................................................................................................................................................. 35

Mode Register ................................................................................................................................................ 38

Burst Length .............................................................................................................................................. 40

Burst Type .................................................................................................................................................. 40

CAS Latency ............................................................................................................................................... 42

Operating Mode ......................................................................................................................................... 42

Write Burst Mode ....................................................................................................................................... 42

Bank/Row Activation ...................................................................................................................................... 43

READ Operation ............................................................................................................................................. 44

WRITE Operation ........................................................................................................................................... 53

Burst Read/Single Write .............................................................................................................................. 60

PRECHARGE Operation .................................................................................................................................. 61

Auto Precharge ........................................................................................................................................... 61

AUTO REFRESH Operation ............................................................................................................................. 73

SELF REFRESH Operation ............................................................................................................................... 75

Power-Down .................................................................................................................................................. 77

Clock Suspend ............................................................................................................................................... 78

PDF: 09005aef80872800

128mb_x32_sdram.pdf - Rev. P 9/11 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

128Mb: x32 SDRAM

Features

List of Figures

Figure 1: 4 Meg x 32 Functional Block Diagram ................................................................................................. 7

Figure 2: 86-Pin TSOP Pin Assignments (Top View) ........................................................................................... 8

Figure 3: 90-Ball FBGA Ball Assignments (Top View) ......................................................................................... 9

Figure 4: 86-Pin Plastic TSOP II (400 mil) – Revision L ..................................................................................... 11

Figure 5: 86-Pin Plastic TSOP II (400 mil) – Package Codes TG/P ...................................................................... 12

Figure 6: 90-Ball VFBGA (8mm x 13mm) ......................................................................................................... 13

Figure 7: Example: Temperature Test Point Location, 54-Pin TSOP (Top View) ................................................. 15

Figure 8: Example: Temperature Test Point Location, 90-Ball VFBGA (Top View) .............................................. 16

Figure 9: ACTIVE Command .......................................................................................................................... 25

Figure 10: READ Command ........................................................................................................................... 26

Figure 11: WRITE Command ......................................................................................................................... 27

Figure 12: PRECHARGE Command ................................................................................................................ 28

Figure 13: Initialize and Load Mode Register .................................................................................................. 37

Figure 14: Mode Register Definition ............................................................................................................... 39

Figure 15: CAS Latency .................................................................................................................................. 42

Figure 16: Example: Meeting

RCD (MIN) When 2 <

RCD (MIN)/

CK < 3 .......................................................... 43

Figure 17: Consecutive READ Bursts .............................................................................................................. 45

Figure 18: Random READ Accesses ................................................................................................................ 46

Figure 19: READ-to-WRITE ............................................................................................................................ 47

Figure 20: READ-to-WRITE With Extra Clock Cycle ......................................................................................... 48

Figure 21: READ-to-PRECHARGE .................................................................................................................. 48

Figure 22: Terminating a READ Burst ............................................................................................................. 49

Figure 23: Alternating Bank Read Accesses ..................................................................................................... 50

Figure 24: READ Continuous Page Burst ......................................................................................................... 51

Figure 25: READ – DQM Operation ................................................................................................................ 52

Figure 26: WRITE Burst ................................................................................................................................. 53

Figure 27: WRITE-to-WRITE .......................................................................................................................... 54

Figure 28: Random WRITE Cycles .................................................................................................................. 55

Figure 29: WRITE-to-READ ............................................................................................................................ 55

Figure 30: WRITE-to-PRECHARGE ................................................................................................................. 56

Figure 31: Terminating a WRITE Burst ............................................................................................................ 57

Figure 32: Alternating Bank Write Accesses ..................................................................................................... 58

Figure 33: WRITE – Continuous Page Burst ..................................................................................................... 59

Figure 34: WRITE – DQM Operation ............................................................................................................... 60

Figure 35: READ With Auto Precharge Interrupted by a READ ......................................................................... 62

Figure 36: READ With Auto Precharge Interrupted by a WRITE ........................................................................ 63

Figure 37: READ With Auto Precharge ............................................................................................................ 64

Figure 38: READ Without Auto Precharge ....................................................................................................... 65

Figure 39: Single READ With Auto Precharge .................................................................................................. 66

Figure 40: Single READ Without Auto Precharge ............................................................................................. 67

Figure 41: WRITE With Auto Precharge Interrupted by a READ ........................................................................ 68

Figure 42: WRITE With Auto Precharge Interrupted by a WRITE ...................................................................... 68

Figure 43: WRITE With Auto Precharge ........................................................................................................... 69

Figure 44: WRITE Without Auto Precharge ..................................................................................................... 70

Figure 45: Single WRITE With Auto Precharge ................................................................................................. 71

Figure 46: Single WRITE Without Auto Precharge ............................................................................................ 72

Figure 47: Auto Refresh Mode ........................................................................................................................ 74

Figure 48: Self Refresh Mode .......................................................................................................................... 76

Figure 49: Power-Down Mode ........................................................................................................................ 77

Figure 50: Clock Suspend During WRITE Burst ............................................................................................... 78

PDF: 09005aef80872800

128mb_x32_sdram.pdf - Rev. P 9/11 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

128Mb: x32 SDRAM

Features

List of Tables

Table 1: Address Table ..................................................................................................................................... 1

Table 2: Key Timing Parameters ....................................................................................................................... 1

Table 3: 128Mb (x32) SDR Part Numbering ....................................................................................................... 1

Table 4: Pin/Ball Descriptions ........................................................................................................................ 10

Table 5: Temperature Limits .......................................................................................................................... 14

Table 6: Thermal Impedance Simulated Values ............................................................................................... 15

Table 7: Absolute Maximum Ratings .............................................................................................................. 17

Table 8: DC Electrical Characteristics and Operating Conditions ..................................................................... 17

Table 9: Capacitance ..................................................................................................................................... 17

Table 10: I

Specifications and Conditions – Revision G ................................................................................ 18

Table 11: I

Specifications and Conditions – Revision L ................................................................................. 19

Table 12: Electrical Characteristics and Recommended AC Operating Conditions ............................................ 20

Table 13: AC Functional Characteristics ......................................................................................................... 22

Table 14: Truth Table – Commands and DQM Operation ................................................................................. 24

Table 15: Truth Table – Current State Bank

Command to Bank

.................................................................. 30

Table 16: Truth Table – Current State Bank n, Command to Bank

................................................................. 32

Table 17: Truth Table – CKE ........................................................................................................................... 34

Table 18: Burst Definition Table ..................................................................................................................... 41

PDF: 09005aef80872800

128mb_x32_sdram.pdf - Rev. P 9/11 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

MT48LC4M32B2F51 Related Products

	MT48LC4M32B2F51	MT48LC4M32B2P-7
Description	4M X 32 SYNCHRONOUS DRAM, 5.5 ns, PDSO86	4M X 32 SYNCHRONOUS DRAM, 5.5 ns, PDSO86
Number of functions	1	1
Number of terminals	86	86
Maximum operating temperature	70 Cel	70 Cel
Minimum operating temperature	0.0 Cel	0.0 Cel
Maximum supply/operating voltage	3.6 V	3.6 V
Minimum supply/operating voltage	3 V	3 V
Rated supply voltage	3.3 V	3.3 V
Minimum access time	5.5 ns	5.5 ns
Processing package description	0.40 INCH, Lead FREE, Plastic, TSOP-86	0.40 INCH, Lead FREE, Plastic, TSOP-86
Lead-free	Yes	Yes
EU RoHS regulations	Yes	Yes
China RoHS regulations	Yes	Yes
state	EOL/LIFEBUY	EOL/LIFEBUY
Craftsmanship	CMOS	CMOS
packaging shape	Rectangle	Rectangle
Package Size	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
surface mount	Yes	Yes
Terminal form	GULL WING	GULL WING
Terminal spacing	0.5000 mm	0.5000 mm
terminal coating	MATTE Tin	MATTE Tin
Terminal location	pair	pair
Packaging Materials	Plastic/Epoxy	Plastic/Epoxy
Temperature level	COMMERCIAL	COMMERCIAL
memory width	32	32
organize	4M × 32	4M × 32
storage density	1.34E8 deg	1.34E8 deg
operating mode	Synchronize	Synchronize
Access method	Four BANK PAGE BURST	Four BANK PAGE BURST
Memory IC type	synchronous dynamic random access memory	synchronous dynamic random access memory
Number of ports	1	1
Number of digits	4M	4M

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