Philips Semiconductors
Product data sheet
Parallel bus to I
2
C-bus controller
PCA9564
DESCRIPTION
The PCA9564 is an integrated circuit designed in CMOS technology
that serves as an interface between most standard parallel-bus
microcontrollers/microprocessors and the serial I
2
C-bus and allows
the parallel bus system to communicate bi-directionally with the
I
2
C-bus. The PCA9564 can operate as a master or a slave and can
be a transmitter or receiver. Communication with the I
2
C-bus is
carried out on a byte-wise basis using interrupt or polled handshake.
The PCA9564 controls all the I
2
C-bus specific sequences, protocol,
arbitration and timing with no external timing element required.
FEATURES
•
Parallel-bus to I
2
C-bus protocol converter and interface
•
Both master and slave functions
•
Multi-master capability
•
Internal oscillator reduces external components
•
Operating supply voltage 2.3 V to 3.6 V
•
5 V tolerant I/Os
•
Standard and fast mode I
2
C capable and compatible with SMBus
•
ESD protection exceeds 2000 V HEM per JESD22-A114,
200 V MM per JESD22-A115, and 1000 V CDM per
JESD22-C101
The PCA9564 is similar to the PCF8584 but operates at lower
voltages and higher I@C frequencies. Other enhancements
requested by design engineers have also been incorporated.
Characteristic
Voltage range
Maximum
master mode
I
2
C frequency
Maximum slave
mode I
2
C
frequency
Clock source
PCA9564
2.3–3.6 V
360 kHz
PCF8584
4.5–5.5 V
90 kHz
Comments
PCA9564 is 5 V
tolerant
Faster I
2
C interface
400 kHz
100 kHz
Faster I
2
C interface
•
Latch-up testing is done to JEDEC Standard JESD78 which
exceed 100 mA.
Internal
External
Less expensive and
more flexible with
internal oscillator
Compatible with
faster processors
•
Packages offered: DIP20, SO20, TSSOP20, HVQFN20
APPLICATIONS
Parallel
interface
Fast
50 MHz
Slow
•
Add I
2
C-bus port to controllers/processors that do not have one
•
Add additional I
2
C-bus ports to controllers/processors that need
multiple I
2
C-bus ports
•
Higher frequency, lower voltage migration path for the PCF8584
•
Converts 8 bits of parallel data to serial data stream to prevent
having to run a large number of traces across the entire PC board
While the PCF8584 supported most parallel-bus microcontrollers/
microprocessors including the Intel 8049/8051, Motorola
6800/68000 and the Zilog Z80, the PCA9564 has been designed to
be very similar to the Philips standard 80C51 microcontroller I
2
C
hardware so the devices are not code compatible. Additionally, the
PCA9564 does not support the bus monitor “Snoop” mode nor the
long distance mode and is not footprint compatible with the
PCF8584.
ORDERING INFORMATION
PACKAGES
20-Pin Plastic DIP
20-Pin Plastic SO
20-Pin Plastic TSSOP
20-Pin Plastic HVQFN
whole wafer
TEMPERATURE RANGE
–40
°C
to +85
°C
–40
°C
to +85
°C
–40
°C
to +85
°C
–40
°C
to +85
°C
–40
°C
to +85
°C
ORDER CODE
PCA9564N
PCA9564D
PCA9564PW
PCA9564BS
PCA9564U
TOPSIDE MARK
PCA9564N
PCA9564D
PCA9564
9564
n/a
DRAWING NUMBER
SOT146-1
SOT163-1
SOT360-1
SOT662-1
n/a
Standard packing quantities and other packaging data are available at www.standardics.philips.com/packaging.
2006 Sep 01
2
Philips Semiconductors
Product data sheet
Parallel bus to I
2
C-bus controller
PCA9564
PIN CONFIGURATION — DIP, SO, TSSOP
D0
D1
D2
D3
D4
D5
D6
D7
DNU
1
2
3
4
5
6
7
8
9
20 V
DD
19 SDA
18 SCL
17 RESET
16 INT
15 A1
PIN CONFIGURATION — HVQFN
16 SDA
15 SCL
14 RESET
13 INT
12 A1
11 A0
CE 10
6
7
8
WR
9
RD
17 V
DD
20 D2
19 D1
V
SS
18 D0
D3
D4
D5
D6
1
2
3
4
5
TOP VIEW
14 A0
13 CE
12 RD
11 WR
D7
V
SS
10
DNU
SW02260
SW02261
PIN DESCRIPTION
PIN NUMBER
DIP, SO, TSSOP
1, 2, 3, 4,
5, 6, 7, 8
9
10
11
HVQFN
1, 2, 3, 4, 5,
18, 19, 20
6
7
1
8
SYMBOL
D0–D7
DNU
V
SS
WR
Pwr
I
PIN
TYPE
I/O
NAME AND FUNCTION
Data Bus:
Bi-directional 3-State data bus used to transfer commands, data and
status between the controller and the CPU. D0 is the least significant bit.
Do not use: must be left floating (pulled LOW internally)
Ground
Write Strobe:
When LOW and CE is also LOW, the contents of the data bus is
loaded into the addressed register. The transfer occurs on the rising edge of the
signal.
Read Strobe:
When LOW and CE is also LOW, causes the contents of the
addressed register to be presented on the data bus. The read cycle begins on the
falling edge of RD.
Chip Enable:
Active-LOW input signal. When LOW, data transfers between the CPU
and the controller are enabled on D0–D7 as controlled by the WR, RD and A0–A1
inputs. When HIGH, places the D0–D7 lines in the 3-State condition.
Address Inputs:
Selects the controller internal registers and ports for read/write
operations.
Interrupt Request:
Active-LOW, open-drain, output. This pin requires a pull-up
device.
Reset:
A LOW level clears internal registers resets the I
2
C state machine.
I
2
C-bus serial clock input/output (open-drain).
I
2
C-bus serial data input/output (open-drain).
Power Supply:
2.3 to 3.6 V
12
9
RD
I
13
10
CE
I
14, 15
16
17
18
19
20
11, 12
13
14
15
16
17
A0, A1
INT
RESET
SCL
SDA
V
DD
I
O
I
I/O
I/O
Pwr
NOTES:
1. HVQFN package die supply ground is connected to both V
SS
pin and exposed center pad. V
SS
pin must be connected to supply ground for
proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board
using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in
the PCB in the thermal pad region.
2006 Sep 01
3
Philips Semiconductors
Product data sheet
Parallel bus to I
2
C-bus controller
PCA9564
FUNCTIONAL DESCRIPTION
General
The PCA9564 acts as an interface device between standard
high-speed parallel buses and the serial I
2
C-bus. On the I
2
C-bus, it
can act either as master or slave. Bidirectional data transfer between
the I
2
C-bus and the parallel-bus microcontroller is carried out on a
byte-wise basis, using either an interrupt or polled handshake.
The Address Register, I2CADR:
I2CADR is not affected by the
SIO hardware. The contents of this register are irrelevant when SIO
is in a master mode. In the slave modes, the seven most significant
bits must be loaded with the microcontroller’s own slave address.
7
I2CADR
BIT7
6
BIT6
5
BIT5
4
BIT4
3
BIT3
2
BIT2
1
BIT1
0
0
own slave address
Internal Oscillator
The PCA9564 contains an internal 9 MHz oscillator which is used
for all I
2
C timing. The oscillator requires up to 500
µs
to start-up
after ENSIO bit is set to “1”.
The most significant bit corresponds to the first bit received from the
I
2
C-bus after a start condition. A logic 1 in I2CADR corresponds to a
HIGH level on the I
2
C-bus, and a logic 0 corresponds to a LOW
level on the bus. The least significant bit is not used but should be
programmed with a ‘0’.
The Data Register, I2CDAT:
I2CDAT contains a byte of serial data
to be transmitted or a byte which has just been received. In master
mode, this includes the slave address that the master wants to send
out on the I
2
C-bus, with the most significant bit of the slave address
in the SD7 bit position and the Read/Write bit in the SD0 bit position.
The CPU can read from and write to this 8-bit register while it is not
in the process of shifting a byte. This occurs when SIO is in a
defined state and the serial interrupt flag is set. Data in I2CDAT
remains stable as long as SI is set. Whenever the SIO generates an
interrupt, the I2CDAT registers contain the data byte that was just
transferred on the I
2
C-bus.
NOTE:
The I2CDAT register will capture the serial address as data
when addressed via the serial bus. Also, the data register will
continue to capture data from the serial bus during 38H so the
I2CDAT register will need to be reloaded when the bus becomes
free.
7
6
SD6
5
SD5
4
SD4
3
SD3
2
SD2
1
SD1
0
SD0
I2CDAT
SD7
Registers
The PCA9564 contains four registers which are used to configure
the operation of the device as well as to send and receive serial data.
The registers are selected by setting pins A0 and A1 to the
appropriate logic levels before a read or write operation is executed.
CAUTION:
Do not write to I
2
C registers while the I
2
C-bus is busy
and the SIO is in master or addressed slave mode.
REGISTER
NAME
I2CSTA
I2CTO
I2CDAT
I2CADR
I2CCON
REGISTER
FUNCTION
Status
Time-out
Data
Own address
Control
A1
0
0
0
1
1
A0
0
0
1
0
1
READ/
WRITE
R
W
R/W
R/W
R/W
DEFAULT
F8h
FFh
00h
00h
00h
The Time-out Register, I2CTO:
The time-out register is used to
determine the maximum time that SCL is allowed to be LOW before
the I
2
C state machine is reset.
When the I
2
C interface is operating, I2CTO is loaded in the time-out
counter at every SCL transition.
7
I2CTO
TE
6
TO6
5
TO5
4
TO4
3
TO3
2
TO2
1
TO1
0
TO0
•
SD7 - SD0:
Eight bits to be transmitted or just received. A logic 1 in I2CDAT
corresponds to a HIGH level on the I
2
C-bus, and a logic 0
corresponds to a LOW level on the bus.
The Control Register, I2CCON:
The microcontroller can read from
and write to this 8-bit register. Two bits are affected by the SIO
hardware: the SI bit is set when a serial interrupt is requested, and
the STO bit is cleared when a STOP condition is present on the
I
2
C-bus. A write to the I2CCON register clears the SI bit and causes
the Serial Interrupt line to be de–asserted and the next clock pulse
on the SCL line to be generated. Since none of the registers should
be written to via the parallel interface once the Serial Interrupt line
has been de-asserted, all the other registers that need to be
modified should be written to before the content of the I2CCON
register is modified.
7
I2CCON
AA
6
ENSIO
5
STA
4
STO
3
SI
2
CR2
1
CR1
0
CR0
Time-out value
The most significant bit of I2CTO (TE) is used as a time-out
enable/disable. A “1” will enable the time-out function. The time-out
period = (I2CTO[6:0] + 1)
×
113.7
µs.
The time-out value may vary
some and is an approximate value.
The time-out register can be used in the following cases:
1. When the SIO, in the master mode, wants to send a START
condition and the SCL line is held LOW by some other device.
The SIO waits a time period equivalent to the time-out value for
the SCL to be released. In case it is not released, the SIO
concludes that there is a bus error, loads 90H in the I2CSTA
register, generates an interrupt signal and releases the SCL and
SDA lines. After the microcontroller reads the status register, it
needs to send an external reset in order to reset the SIO.
2. In the master mode, the time-out feature starts every time the SCL
goes LOW. If SCL stays LOW for a time period equal to or greater
than the time-out value, the SIO concludes there is a bus error
and behaves in the manner described above.
3. In case of a forced access to the I
2
C-bus. (See more details on
page 15.)
•
ENSIO
, THE
SIO E
NABLE
B
IT
ENSIO = “0”: When ENSIO is “0”, the SDA and SCL outputs are in a
high impedance state. SDA and SCL input signals are ignored, SIO
is in the “not addressed” slave state.
ENSIO = “1”: When ENSIO is “1”, SIO is enabled.
After the ENSIO bit is set, it takes 500
µs
for the internal oscillator to
start up, therefore, the PCA9564 will enter either the master or the
slave mode after this time. ENSIO should not be used to temporarily
2006 Sep 01
5
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