71V424L10PH datasheet, PDF - EEWORLD Datasheet

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71V424L10PH: DescriptionStandard SRAM, 512KX8, 10ns, CMOS, PDSO44; Categorystorage storage; File Size128KB，9 Pages; ManufacturerIDT (Integrated Device Technology)

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71V424L10PH Overview

Standard SRAM, 512KX8, 10ns, CMOS, PDSO44

71V424L10PH Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
package instruction	TSOP, TSOP44,.46,32
Reach Compliance Code	_compli
Maximum access time	10 ns
I/O type	COMMON
JESD-30 code	R-PDSO-G44
JESD-609 code	e0
memory density	4194304 bi
Memory IC Type	STANDARD SRAM
memory width	8
Humidity sensitivity level	3
Number of terminals	44
word count	524288 words
character code	512000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	512KX8
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP
Encapsulate equivalent code	TSOP44,.46,32
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	240
power supply	3.3 V
Certification status	Not Qualified
Maximum standby current	0.01 A
Minimum standby current	3 V
Maximum slew rate	0.165 mA
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
Base Number Matches	1

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3.3V CMOS Static RAM

4 Meg (512K x 8-Bit)

Features

Description

IDT71V424S/YS

IDT71V424L/YL

◆

512K x 8 advanced high-speed CMOS Static RAM

JEDEC Center Power / GND pinout for reduced noise

Equal access and cycle times

— Commercial and Industrial: 10/12/15ns

Single 3.3V power supply

One Chip Select plus one Output Enable pin

Bidirectional data inputs and outputs directly

TTL-compatible

Low power consumption via chip deselect

Available in 36-pin, 400 mil plastic SOJ package and

44-pin, 400 mil TSOP.

The IDT71V424 is a 4,194,304-bit high-speed Static RAM organized

as 512K x 8. It is fabricated using IDT’s high-perfomance, high-reliability

CMOS technology. This state-of-the-art technology, combined with inno-

vative circuit design techniques, provides a cost-effective solution for high-

speed memory needs.

The IDT71V424 has an output enable pin which operates as fast as

5ns, with address access times as fast as 10ns. All bidirectional inputs and

outputs of the IDT71V424 are TTL-compatible and operation is from a

single 3.3V supply. Fully static asynchronous circuitry is used, requiring

no clocks or refresh for operation.

The IDT71V424 is packaged in a 36-pin, 400 mil Plastic SOJ and 44-

pin, 400 mil TSOP.

Functional Block Diagram

•

ADDRESS

DECODER

•

4,194,304-BIT

MEMORY ARRAY

I/O

- I/O

I/O CONTROL

CONTROL

LOGIC

3622 drw 01

JUNE 2009

Integrated Device Technology, Inc.

DSC-3622/09

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