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A1425A-PG133B

Description
FPGA, 547 CLBS, 2000 GATES, 37 MHz, CQFP84
CategoryProgrammable logic devices    Programmable logic   
File Size546KB,98 Pages
ManufacturerActel
Websitehttp://www.actel.com/
Download Datasheet Parametric View All

A1425A-PG133B Overview

FPGA, 547 CLBS, 2000 GATES, 37 MHz, CQFP84

A1425A-PG133B Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerActel
package instructionCERAMIC, PGA-133
Reach Compliance Codeunknow
Other featuresMAX 100 I/OS
maximum clock frequency100 MHz
Combined latency of CLB-Max3.5 ns
JESD-30 codeS-CPGA-P133
JESD-609 codee0
length34.544 mm
Configurable number of logic blocks310
Equivalent number of gates2500
Number of entries100
Number of logical units310
Output times100
Number of terminals133
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize310 CLBS, 2500 GATES
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codePGA
Encapsulate equivalent codePGA133M,13X13
Package shapeSQUARE
Package formGRID ARRAY
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Programmable logic typeFIELD PROGRAMMABLE GATE ARRAY
Certification statusNot Qualified
Filter levelMIL-STD-883 Class B
Maximum seat height4.826 mm
Maximum supply voltage5.5 V
Minimum supply voltage4.5 V
Nominal supply voltage5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formPIN/PEG
Terminal pitch2.54 mm
Terminal locationPERPENDICULAR
Maximum time at peak reflow temperatureNOT SPECIFIED
width34.544 mm
v3.0
HiRel FPGAs
Fe a t ur es
• Low-Power 0.8µ CMOS Technology
32 0 0D X Fe a t ur es
• Highly Predictable Performance with 100% Automatic
Placement and Routing
• Device Sizes from 1,200 to 20,000 Gates
• Up to 6 Fast, Low-Skew Clock Networks
• Up to 202 User-Programmable I/O Pins
More Than 500 Macro Functions
Up to 1,276 Dedicated Flip-Flops
I/O Drive to 10 mA
Devices Available to DSCC SMD
CQFP and CPGA Packaging
Nonvolatile, User Programmable
Logic Fully Tested Prior to Shipment
100% Military Temperature Tested (–55°C to +125°C)
QML Certified Devices
• 100 MHz System Logic Integration
• Highest Speed FPGA SRAM, up to 2.5 kbits Configurable
Dual-Port SRAM
• Fast Wide-Decode Circuitry
• Low-Power 0.6µ CMOS Technology
12 0 0X L Fe at ure s
• Pin for Pin Compatible with ACT 2
• System Performance to 50 MHz over Military Temperature
• Low-Power 0.6µ CMOS Technology
A CT 2 Fe at ure s
• Proven Reliability Data Available
• Successful Military/Avionics Supplier for Over 10 Years
A CT 3 Fe at ure s
• Best-Value, High-Capacity FPGA Family
• System Performance to 40 MHz over Military Temperature
• Low-Power 1.0µ CMOS Technology
A CT 1 Fe at ure s
• Highest-Performance, Highest-Capacity FPGA Family
• System Performance to 60 MHz over Military Temperature
• Lowest-Cost FPGA Family
• System Performance to 20 MHz over Military Temperature
• Low-Power 1.0µ CMOS Technology
Pr od uc t F am i l y P r o f i l e
(more devices on
page 2)
Family
Device
Capacity
System Gates
Logic Gates
SRAM Bits
Logic Modules
S-Modules
C-Modules
Decode
Flip-Flops (Maximum)
User I/Os (Maximum)
Performance
System Speed (maximum)
Packages (by Pin Count)
CPGA
CQFP
3200DX
A32100DX
15,000
10,000
2,048
1,362
700
662
20
738
152
55 MHz
A32200DX
30,000
20,000
2,560
2,414
1,230
1,184
24
1,276
202
55 MHz
A1425A
3,750
2,500
NA
310
160
150
NA
435
100
60 MHz
133
132
ACT 3
A1460A
9,000
6,000
NA
848
432
416
NA
976
168
60 MHz
207
196
A14100A
15,000
10,000
NA
1,377
697
680
NA
1,493
228
60 MHz
257
256
1200XL
A1280XL
12,000
8,000
1,232
624
608
NA
998
140
50 MHz
176
172
84
208, 256
J an u a r y 2 0 0 0
1
© 2000 Actel Corporation
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