AN400
T
ABLE O F
C
ONTENTS
Section
Page
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
2. Si474x 4x4 mm QFN Schematic and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2.1. Si474x 4x4 mm Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2.2. Si474x 4x4 mm Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2.3. Si474x 4x4 mm Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2.4. Si474x 4x4 mm Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.5. Si474x 4x4 mm Design Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3. Whip Antenna for FM/WB Receiver (Si4740/41/42/43/44/45 Only) . . . . . . . . . . . . . . . . . 10
3.1. FM/WB Whip Antenna Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2. FM/WB Whip Antenna Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.3. FM/WB Whip Antenna Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.4. FM/WB Whip Antenna Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.5. FM/WB Whip Antenna Design Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4. Whip Antenna for RDS Receiver (Si4749 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1. Whip Antenna Schematic for RDS Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2. Whip Antenna for RDS receiver Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
4.3. Whip Antenna Layout for RDS Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.4. Whip Antenna Design Checklist for RDS Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5. Whip Antenna for AM/LW Receiver (Si4740/41/42/43/44/45 Only) . . . . . . . . . . . . . . . . . 15
5.1. AM/LW Whip Antenna Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2. AM/LW Whip Antenna Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
5.3. AM/LW Whip Antenna Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
5.4. AM/LW Whip Antenna Design Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6. Whip Antenna for AM/LW/SW Receiver (Si4742/43/44/45 only) . . . . . . . . . . . . . . . . . . . 18
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Rev. 0.5
3
AN400
2. Si474x 4x4 mm QFN Schematic and Layout
This section describes the minimum schematic and layout options required for optimal Si474x performance.
Population options are provided to support layouts for different audio output options and mitigation of system noise.
2.1. Si474x 4x4 mm Design
C1 (22 nF) is a required bypass capacitor for VDD supply pin 13. Place C1 as close as possible to VDD pin 13 and
GND pin 14. Place a VIA connecting C1 VDD supply to the power rail such that the cap is closer to the Si474x than
the VIA. Route C1 GND directly and only to GND pin 14 with a wide, low-inductance trace. These
recommendations are made to reduce the size of the current loop created by the bypass cap and routing, minimize
bypass cap impedance, and return all currents to the GND pad.
C13 (22 nF), C17 (100 µF), and C19 (0.1 µF) are optional bypass capacitors for the VIO supply pin 12 and may be
placed to mitigate supply noise. Place C13, C17, and C19 as close as possible to the VIO pin 12 and the GND pin
14. Place VIAs connecting C13, C17, and C19 VIO supply to the power rail such that the capacitors are closer to
the Si474x than the VIAs. Route C13, C17, and C19 GND directly and only to GND pin 14 with wide, low-
inductance traces. These recommendations are made to reduce the size of the current loop created by the bypass
capacitors and routing, minimize bypass cap impedance, and return all currents to the GND pad.
C2 (2 pF) is a required shunt capacitor from the DFS pin to ground when using digital audio output (Si4741/43/45
only), and is used to prevent degradation of audio quality. Place the capacitor as close as possible to the DFS pin.
C6 (0.1 µF) and C18 (100 µF) are optional bypass capacitors to mitigate system noise in AM and FM frequencies.
Route them the same way as C1.
C8 and C9 (0.39 µF) are ac coupling capacitors for analog audio output from ROUT pin 15 and LOUT pin 16. The
input resistance of the amplifier and the capacitor will set the high-pass pole given by Equation 1. Placement
location is not critical.
1
-
f
c
= ---------------
2RC
Equation 1. High-Pass Pole Calculation
R12, R14, R26, R29, and R30 (25
to 2 k) are optional series termination resistors used to mitigate system
noise. The recommended value of the resistors is 2 k for optimal edge rate and noise suppression. Confirm that
timing requirements are met with the selected series termination resistor value. Place the series termination
resistors, R12, R14, R21, R24, R26, R29, and R30, as close to the host controller as possible.
R21 and R24 (25
to 2 k) are optional series termination resistors used to mitigate system noise. The
recommended value of the resistors is 2 k for optimal edge rate and noise suppression. Confirm that timing
requirements are met with the selected series termination resistor value. Place the series termination resistors,
R21 and R24 as close to the chip input as possible.
R17 and R20 (22 k) are optional pull-up resistors for the RSTB and SENB lines. The size of pull-up resistor value
will vary based on the number of devices, capacitance, and speed of the bus. Placement location is not critical.
R27 and R28 (22 k) are optional pull-up resistors for the SCLK and SDIO lines required only when using an I2C
bus. The size of pull-up resistor value will vary based on the number of devices, capacitance, and speed of the bus.
Placement location is not critical. Refer to the I2C specification for additional design information.
R16 (25
to
2 k) is a required series termination resistor when using digital audio output (Si4741/43/45 only) and
is used to mitigate noise from the digital data routed from DOUT pin 17. The recommended value of the resistor is
604
for optimal edge rate and noise suppression. Confirm that timing requirements are met with the selected
series termination resistor value. Place R16 as close to pin 17 as possible.
R15 (25
to
2 k) is a required series termination resistor when using digital audio (Si4741/43/45 only) and is
used to mitigate noise from the digital clock routed to GPO3/DCLK pin 19. The recommended value of the resistor
is 2 k for optimal edge rate and noise suppression. Confirm that timing requirements are met with the selected
series termination resistor value. Place R15 as close to the host controller as possible. Choosing a DCLK
frequency that is above the AM band reduces the chances of having DCLK harmonics that fall in the AM band and
create digital noise.
4
Rev. 0.5
AN400
R11 (25
to
2 k) is a required series termination resistor when using digital audio output (Si4741/43/45 only) and
is used to mitigate noise from the digital frame clock routed to DFS pin 18. The recommended value of the resistor
is 1.4 k for optimal edge rate and noise suppression. Confirm that timing requirements are met with the selected
series termination resistor value. Place R11 as close to the host controller as possible.
R22 and R23 (4.02 k) are optional pull-up and pull-down resistors for the RCLK line to reduce the energy in
harmonics of RCLK that might fall in the AM band. The recommended value is chosen such that RCLK will still
meet the voltage requirements of Si474x. Place R22 and R23 as close as possible to RCLK pin 11. If the RCLK
frequency is higher than the maximum frequency in the AM band, this will eliminate harmonics of RCLK that fall in
the AM band. Refer to “AN332: Si47xx Programming Guide” and “AN344: Si4706/07/4x Programming Guide” for
recommended RCLK and prescalar values.
R2 (24.3 k) and R13 (4.53 k) are optional pull-up and pull-down resistors for the DFS line when using digital
audio output (Si4741/43/45 only.) They are used to reduce the energy in harmonics of DFS that might fall in the AM
band. The recommended value is chosen such that DFS will still meet the voltage and timing requirements of I2S.
Place R2 and R13 as close as possible to DFS pin 18.
2.2. Si474x 4x4 mm Schematic
Figure 1. Si474x 4x4 mm QFN Schematic
Rev. 0.5
5
FPGA/CPLD
京公网安备 11010802033920号
EEWORLD
