8N4Q001EG-2060CD8 datasheet, PDF

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8N4Q001EG-2060CD8: DescriptionLVDS Output Clock Oscillator; CategoryPassive components oscillator; File Size188KB，19 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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8N4Q001EG-2060CD8 Overview

LVDS Output Clock Oscillator

8N4Q001EG-2060CD8 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Reach Compliance Code	compliant
Other features	ENABLE/DISABLE FUNCTION; DIFFERENTIAL OUTPUT; TR
maximum descent time	0.425 ns
Frequency Adjustment - Mechanical	NO
frequency stability	50%
JESD-609 code	e3
Installation features	SURFACE MOUNT
Nominal operating frequency	622.08 MHz
Maximum operating temperature	70 °C
Minimum operating temperature
Oscillator type	LVDS
physical size	7.0mm x 5.0mm x 1.55mm
longest rise time	0.425 ns
Maximum supply voltage	3.465 V
Minimum supply voltage	3.135 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Matte Tin (Sn)

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Quad-Frequency Programmable XO IDT8N4Q001 REV G

DATA SHEET

General Description

The IDT8N4Q001 is a Quad-Frequency Programmable Clock

Oscillator with very flexible frequency programming capabilities. The

device uses IDT’s fourth generation FemtoClock® NG technology for

an optimum high clock frequency and low phase noise performance.

The device accepts 2.5V or 3.3V supply and is packaged in a small,

lead-free (RoHS 6) 10-lead ceramic 5mm x 7mm x 1.55mm package.

Besides the four default power-up frequencies set by the FSEL0 and

FSEL1 pins, the IDT8N4Q001 can be programmed via the I

interface to output clock frequencies between 15.476MHz to

866.67MHz and from 975MHz to 1,300MHz to a very high degree of

precision with a frequency step size of 435.9Hz ÷

(N is the PLL

output divider). Since the FSEL0 and FSEL1 pins are mapped to four

independent PLL divider registers (P, MINT, MFRAC and N),

reprogramming those registers to other frequencies under control of

FSEL0 and FSEL1 is supported. The extended temperature range

supports wireless infrastructure, telecommunication and networking

end equipment requirements.

Features

•

Fourth generation FemtoClock® NG technology

Programmable clock output frequency from 15.476MHz to

866.67MHz and from 975MHz to 1,300MHz

Four power-up default frequencies (see part number order

codes), re-programmable by I

C programming interface for the output clock frequency and

internal PLL control registers

Frequency programming resolution is 435.9Hz ÷N

One 2.5V, 3.3V LVDS clock output

Two control inputs for the power-up default frequency

LVCMOS/LVTTL compatible control inputs

RMS phase jitter @ 156.25MHz (12kHz - 20MHz): 0.253ps

(typical), integer PLL feedback configuration

RMS phase jitter @ 156.25MHz (1kHz - 40MHz): 0.263ps

(typical), integer PLL feedback configuration

Full 2.5V or 3.3V supply modes

-40°C to 85°C ambient operating temperature

Available in Lead-free (RoHS 6) package

Block Diagram

OSC

XTAL

÷MINT,

MFRAC

FSEL1

FSEL0

SCLK

SDATA

Pulldown

Pullup

Pin Assignment

÷P

PFD

LPF

FemtoClock® NG

VCO

1950-2600MHz

÷N

Q

DNU 1

OE 2

GND 3

FSEL0 4

FSEL1 5

10 SCLK

9 SDATA

8 V

7 nQ

6 Q

Configuration Register (ROM)

(Frequency, APR, Polarity)

C Control

IDT8N4Q001

10-lead ceramic 5mm x 7mm x 1.55mm

package body

CD Package

Top View

IDT8N4Q001GCD

REVISION A

FEBRUARY 21, 2012

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