Micron Confidential and Proprietary
64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous
NAND
Features
NAND Flash Memory
MT29F64G08CBAA[A/B], MT29F128G08C[E/F]AAA, MT29F128G08CFAAB,
MT29F256G08C[J/K/M]AAA, MT29F256G08CJAAB, MT29F512G08CUAAA,
MT29F64G08CBCAB, MT29F128G08CECAB, MT29F256G08C[K/M]CAB,
MT29F512G08CUCAB
Features
• Open NAND Flash Interface (ONFI) 2.2-compliant
1
• Multiple-level cell (MLC) technology
• Organization
– Page size x8: 8640 bytes (8192 + 448 bytes)
– Block size: 256 pages (2048K + 112K bytes)
– Plane size: 2 planes x 2048 blocks per plane
– Device size: 64Gb: 4096 blocks;
128Gb: 8192 blocks;
256Gb: 16,384 blocks;
512Gb: 32,786 blocks
• Synchronous I/O performance
– Up to synchronous timing mode 5
2
– Clock rate: 10ns (DDR)
– Read/write throughput per pin: 200 MT/s
• Asynchronous I/O performance
– Up to asynchronous timing mode 5
–
t
RC/
t
WC: 20ns (MIN)
– Up to asynchronous timing mode 5
– Read/write throughput per pin: 50 MT/s
• Array performance
– Read page: 75µs (MAX)
– Program page: 1300µs (TYP)
– Erase block: 3.8ms (TYP)
• Operating Voltage Range
– V
CC
: 2.7–3.6V
– V
CCQ
: 1.7–1.95V, 2.7–3.6V
• Command set: ONFI NAND Flash Protocol
• Advanced Command Set
– Program cache
– Read cache sequential
– Read cache random
– One-time programmable (OTP) mode
– Multi-plane commands
– Multi-LUN operations
– Read unique ID
– Copyback
• First block (block address 00h) is valid when ship-
ped from factory. For minimum required ECC, see
Error Management (page 111).
• RESET (FFh) required as first command after pow-
er-on
• Operation status byte provides software method for
detecting
– Operation completion
– Pass/fail condition
– Write-protect status
• Data strobe (DQS) signals provide a hardware meth-
od for synchronizing data DQ in the synchronous
interface
• Copyback operations supported within the plane
from which data is read
• Quality and reliability
– Data retention: JESD47G compliant; see qualifi-
cation report
– Endurance: 3000 PROGRAM/ERASE cycles
• Operating temperature:
– Commercial: 0°C to +70°C
– Industrial (IT): –40ºC to +85ºC
• Package
– 52-pad LGA
– 48-pin TSOP
– 100-ball BGA
Notes:
1. The ONFI 2.2 specification is available at
www.onfi.org.
2. BGA devices up to Synchronous timing
mode 5. TSOP devices up to Synchronous
timing mode 4.
PDF: 09005aef83d2277a
L74A_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. F 5/12 EN
1
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2009 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous
NAND
Features
Part Numbering Information
Micron NAND Flash devices are available in different configurations and densities. Verify valid part numbers by
using Micron’s part catalog search at
www.micron.com.
To compare features and specifications by device type,
visit
www.micron.com/products.
Contact the factory for devices not found.
Figure 1: Part Numbering
MT 29F 64G 08
Micron Technology
NAND Flash
29F = NAND Flash memory
C
B
A
A
A WP
Z
ES
:A
Design Revision
A = First revision
Production Status
Blank = Production
ES = Engineering sample
Density
64G = 64Gb
128G = 128Gb
256G = 256Gb
512G = 512Gb
Reserved for Future Use
Blank
Blank = Polyimide Process Not Applied
Z = Polyimide Process Applied
Wafer Process Applied
08 = 8 bits
Device Width
Level
Bit/Cell
C
2-bit
Blank = Commercial (0°C to +70°C)
IT = Industrial (–40°C to +85°C)
Operating Temperature Range
Speed Grade (synchronous mode only)
-12 = 166 MT/s
-10 = 200 MT/s
Classification
B
E
F
J
K
M
U
Die # of CE# # of R/B#
I/O
1
1
1
Common
2
2
4
4
4
8
2
2
2
2
4
4
2
2
2
2
4
4
Separate
Common
Common
Separate
Separate
Separate
C5 = 52-pad VLGA 14mm x 18mm x 1.0mm
1
H1 = 100-ball VBGA 12mm x 18mm x 1.0mm
1
H2 = 100-ball TBGA 12mm x 18mm x 1.2mm
1
H3 = 100-ball LBGA 12mm x 18mm x 1.4mm
1
WP = 48-pin TSOP
1
(CPL)
Package Code
A = V
CC
: 3.3V (2.7–3.6V), V
CCQ
: 3.3V (2.7–3.6V)
C = V
CC
: 3.3V (2.7–3.6V), V
CCQ
: 1.8V (1.7–1.95V)
Operating Voltage Range
A = Async only
B = Sync/Async
Interface
Generation Feature Set
A = First set of device features
Note:
1. Pb-free package.
PDF: 09005aef83d2277a
L74A_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. F 5/12 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2009 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous
NAND
Features
Contents
General Description ......................................................................................................................................... 9
Asynchronous and Synchronous Signal Descriptions ......................................................................................... 9
Signal Assignments ......................................................................................................................................... 11
Package Dimensions ....................................................................................................................................... 15
Architecture ................................................................................................................................................... 20
Device and Array Organization ........................................................................................................................ 21
Bus Operation – Asynchronous Interface ......................................................................................................... 28
Asynchronous Enable/Standby ................................................................................................................... 28
Asynchronous Bus Idle ............................................................................................................................... 28
Asynchronous Commands .......................................................................................................................... 29
Asynchronous Addresses ............................................................................................................................ 30
Asynchronous Data Input ........................................................................................................................... 31
Asynchronous Data Output ......................................................................................................................... 32
Write Protect .............................................................................................................................................. 33
Ready/Busy# .............................................................................................................................................. 33
Bus Operation – Synchronous Interface ........................................................................................................... 38
Synchronous Enable/Standby ..................................................................................................................... 39
Synchronous Bus Idle/Driving .................................................................................................................... 39
Synchronous Commands ............................................................................................................................ 40
Synchronous Addresses .............................................................................................................................. 41
Synchronous DDR Data Input ..................................................................................................................... 42
Synchronous DDR Data Output .................................................................................................................. 43
Write Protect .............................................................................................................................................. 45
Ready/Busy# .............................................................................................................................................. 45
Device Initialization ....................................................................................................................................... 46
Activating Interfaces ....................................................................................................................................... 48
Activating the Asynchronous Interface ........................................................................................................ 48
Activating the Synchronous Interface .......................................................................................................... 48
Command Definitions .................................................................................................................................... 50
Reset Operations ............................................................................................................................................ 52
RESET (FFh) ............................................................................................................................................... 52
SYNCHRONOUS RESET (FCh) .................................................................................................................... 53
RESET LUN (FAh) ....................................................................................................................................... 54
Identification Operations ................................................................................................................................ 55
READ ID (90h) ............................................................................................................................................ 55
READ ID Parameter Tables .......................................................................................................................... 56
READ PARAMETER PAGE (ECh) .................................................................................................................. 57
Parameter Page Data Structure Tables ..................................................................................................... 58
READ UNIQUE ID (EDh) ............................................................................................................................ 69
Configuration Operations ............................................................................................................................... 70
SET FEATURES (EFh) .................................................................................................................................. 70
GET FEATURES (EEh) ................................................................................................................................. 71
Status Operations ........................................................................................................................................... 75
READ STATUS (70h) ................................................................................................................................... 76
READ STATUS ENHANCED (78h) ................................................................................................................ 77
Column Address Operations ........................................................................................................................... 78
CHANGE READ COLUMN (05h-E0h) .......................................................................................................... 78
CHANGE READ COLUMN ENHANCED (06h-E0h) ....................................................................................... 79
CHANGE WRITE COLUMN (85h) ................................................................................................................ 80
CHANGE ROW ADDRESS (85h) ................................................................................................................... 81
PDF: 09005aef83d2277a
L74A_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. F 5/12 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2009 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous
NAND
Features
Read Operations ............................................................................................................................................. 83
READ MODE (00h) ..................................................................................................................................... 85
READ PAGE (00h-30h) ................................................................................................................................ 86
READ PAGE CACHE SEQUENTIAL (31h) ...................................................................................................... 87
READ PAGE CACHE RANDOM (00h-31h) .................................................................................................... 88
READ PAGE CACHE LAST (3Fh) .................................................................................................................. 90
READ PAGE MULTI-PLANE (00h-32h) ......................................................................................................... 91
Program Operations ....................................................................................................................................... 93
PROGRAM PAGE (80h-10h) ......................................................................................................................... 93
PROGRAM PAGE CACHE (80h-15h) ............................................................................................................. 95
PROGRAM PAGE MULTI-PLANE (80h-11h) ................................................................................................. 97
Erase Operations ............................................................................................................................................ 99
ERASE BLOCK (60h-D0h) ............................................................................................................................ 99
ERASE BLOCK MULTI-PLANE (60h-D1h) ................................................................................................... 100
Copyback Operations .................................................................................................................................... 101
COPYBACK READ (00h-35h) ...................................................................................................................... 102
COPYBACK PROGRAM (85h–10h) .............................................................................................................. 103
COPYBACK READ MULTI-PLANE (00h-32h) ............................................................................................... 103
COPYBACK PROGRAM MULTI-PLANE (85h-11h) ....................................................................................... 104
One-Time Programmable (OTP) Operations ................................................................................................... 105
PROGRAM OTP PAGE (80h-10h) ................................................................................................................ 106
PROTECT OTP AREA (80h-10h) .................................................................................................................. 107
READ OTP PAGE (00h-30h) ........................................................................................................................ 108
Multi-Plane Operations ................................................................................................................................. 109
Multi-Plane Addressing ............................................................................................................................. 109
Interleaved Die (Multi-LUN) Operations ......................................................................................................... 110
Error Management ........................................................................................................................................ 111
Shared Pages ................................................................................................................................................. 112
Output Drive Impedance ............................................................................................................................... 114
AC Overshoot/Undershoot Specifications ....................................................................................................... 117
Synchronous Input Slew Rate ......................................................................................................................... 118
Output Slew Rate ........................................................................................................................................... 119
Electrical Specifications ................................................................................................................................. 120
Electrical Specifications – DC Characteristics and Operating Conditions (Asynchronous) ................................. 122
Electrical Specifications – DC Characteristics and Operating Conditions (Synchronous) ................................... 123
Electrical Specifications – DC Characteristics and Operating Conditions (V
CCQ
) ............................................... 123
Electrical Specifications – AC Characteristics and Operating Conditions (Asynchronous) ................................. 124
Electrical Specifications – AC Characteristics and Operating Conditions (Synchronous) ................................... 126
Electrical Specifications – Array Characteristics .............................................................................................. 129
Asynchronous Interface Timing Diagrams ...................................................................................................... 130
Synchronous Interface Timing Diagrams ........................................................................................................ 141
Revision History ............................................................................................................................................ 163
Rev. F Production – 5/12 ............................................................................................................................ 163
Rev. E Production – 3/11 ............................................................................................................................ 163
Rev. D Production – 12/10 .......................................................................................................................... 163
Rev. C – 7/10 .............................................................................................................................................. 163
Rev. B – 2/10 .............................................................................................................................................. 163
Rev. A – 11/09 ............................................................................................................................................ 164
PDF: 09005aef83d2277a
L74A_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. F 5/12 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2009 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous
NAND
Features
List of Tables
Table 1: Asynchronous and Synchronous Signal Definitions .............................................................................. 9
Table 2: Array Addressing for Logical Unit (LUN) ............................................................................................ 27
Table 3: Asynchronous Interface Mode Selection ............................................................................................ 28
Table 4: Synchronous Interface Mode Selection .............................................................................................. 38
Table 5: Command Set .................................................................................................................................. 50
Table 6: Read ID Parameters for Address 00h .................................................................................................. 56
Table 7: Read ID Parameters for Address 20h .................................................................................................. 56
Table 8: Parameter Page Data Structure .......................................................................................................... 58
Table 9: Feature Address Definitions .............................................................................................................. 70
Table 10: Feature Address 01h: Timing Mode .................................................................................................. 72
Table 11: Feature Addresses 10h and 80h: Programmable Output Drive Strength .............................................. 73
Table 12: Feature Addresses 81h: Programmable R/B# Pull-Down Strength ...................................................... 73
Table 13: Feature Addresses 90h: Array Operation Mode ................................................................................. 74
Table 14: Status Register Definition ................................................................................................................ 75
Table 15: OTP Area Details ............................................................................................................................ 106
Table 16: Error Management Details ............................................................................................................. 111
Table 17: Shared Pages ................................................................................................................................. 112
Table 18: Output Drive Strength Conditions (V
CCQ
= 1.7–1.95V) ...................................................................... 114
Table 19: Output Drive Strength Impedance Values (V
CCQ
= 1.7–1.95V) ........................................................... 114
Table 20: Output Drive Strength Conditions (V
CCQ
= 2.7–3.6V) ....................................................................... 115
Table 21: Output Drive Strength Impedance Values (V
CCQ
= 2.7–3.6V) ............................................................ 115
Table 22: Pull-Up and Pull-Down Output Impedance Mismatch ..................................................................... 116
Table 23: Asynchronous Overshoot/Undershoot Parameters .......................................................................... 117
Table 24: Synchronous Overshoot/Undershoot Parameters ............................................................................ 117
Table 25: Test Conditions for Input Slew Rate ................................................................................................ 118
Table 26: Input Slew Rate (V
CCQ
= 1.7–1.95V) ................................................................................................. 118
Table 27: Input Slew Rate (V
CCQ
= 2.7–3.6V) ................................................................................................... 118
Table 28: Test Conditions for Output Slew Rate .............................................................................................. 119
Table 29: Output Slew Rate (V
CCQ
= 1.7–1.95V) ............................................................................................... 119
Table 30: Output Slew Rate (V
CCQ
= 2.7–3.6V) ................................................................................................ 119
Table 31: Absolute Maximum Ratings by Device ............................................................................................ 120
Table 32: Recommended Operating Conditions ............................................................................................. 120
Table 33: Valid Blocks per LUN ...................................................................................................................... 120
Table 34: Capacitance: 100-Ball BGA Package ................................................................................................ 121
Table 35: Capacitance: 48-Pin TSOP Package ................................................................................................. 121
Table 36: Capacitance: 52-Pad LGA Package .................................................................................................. 121
Table 37: Test Conditions .............................................................................................................................. 122
Table 38: DC Characteristics and Operating Conditions (Asynchronous Interface) .......................................... 122
Table 39: DC Characteristics and Operating Conditions (Synchronous Interface) ............................................ 123
Table 40: DC Characteristics and Operating Conditions (3.3V V
CCQ
) ............................................................... 123
Table 41: DC Characteristics and Operating Conditions (1.8V V
CCQ
) ............................................................... 124
Table 42: AC Characteristics: Asynchronous Command, Address, and Data ..................................................... 124
Table 43: AC Characteristics: Synchronous Command, Address, and Data ...................................................... 126
Table 44: Array Characteristics ...................................................................................................................... 129
PDF: 09005aef83d2277a
L74A_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. F 5/12 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2009 Micron Technology, Inc. All rights reserved.
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