3N166
P-CHANNEL MOSFET
The 3N166 is a monolithic dual enhancement mode P-Channel Mosfet
FEATURES
DIRECT REPLACEMENT FOR INTERSIL 3N166
ABSOLUTE MAXIMUM RATINGS
1
@ 25°C (unless otherwise noted)
Maximum Temperatures
The hermetically sealed TO-78 package is well suited
Storage Temperature
‐65°C to +200°C
for high reliability and harsh environment applications.
Operating Junction Temperature
‐55°C to +150°C
Lead Temperature (Soldering, 10 sec.)
+300°C
(See Packaging Information).
Maximum Power Dissipation
Continuous Power Dissipation (one side)
300mW
3N166 Features:
Total Derating above 25°C
4.2 mW/°C
MAXIMUM CURRENT
Very high Input Impedance
Drain Current
50mA
Low Capacitance
MAXIMUM VOLTAGES
High Gain
High Gate Breakdown Voltage
Drain to Gate or Drain to Source
2
‐30V
3
Low Threshold Voltage
Peak Gate to Source
±125V
Gate‐Gate Voltage
±80V
3N166 ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted)
SYMBOL
CHARACTERISTIC
MIN
TYP.
MAX
UNITS
CONDITIONS
I
GSSR
Gate Reverse Leakage Current
‐‐
‐‐
10
V
GS
= ‐0V
I
GSSF
Gate Forward Current
‐‐
‐‐
‐10
V
GS
= ‐40V
pA
T
A
= +125°C
‐‐
‐‐
‐25
I
DSS
Drain to Source Leakage Current
‐‐
‐‐
‐200
V
DS
= ‐20V
I
SDS
Source to Drain Leakage Current
‐‐
‐‐
‐400
V
SD
= ‐20V V
DB
= 0
I
D(on)
Drain Current “On”
‐5.0
‐‐
‐30
mA
V
DS
= ‐15V, V
GS
= ‐10V
V
GS(th)
Gate to Source Threshold Voltage
‐2.0
‐‐
‐5.0
V
V
DS
= ‐15V, I
D
= ‐10µA
‐2.0
‐‐
‐5.0
V
DS
= V
GS
, I
D
= ‐10µA
r
DS(on)
Drain to Source “On” Resistance
‐‐
‐‐
300
Ω
V
GS
= ‐20V, I
D
= ‐100µA
g
fs
Forward Transconductance
1500
‐‐
3000
µS
V
DS
= ‐15V, I
D
= ‐10mA , f = 1kHz
The 3N166 is a dual enhancement mode P-Channel
Mosfet and is ideal for space constrained applications
and those requiring tight electrical matching.
g
os
C
iss
C
rss
C
oss
R
E
(Y
fs
)
Input Capacitance
‐‐
‐‐
3
pF
V
DS
= ‐15V, I
D
= ‐10mA , f = 1MHz
4
Reverse Transfer Capacitance
‐‐
‐‐
0.7
Output Capacitance
‐‐
‐‐
3.0
Common Source Forward
1200
‐‐
‐‐
µS
V
DS
= ‐15V, I
D
= ‐10mA , f = 100MHz
4
Transconductance
MATCHING CHARACTERISTICS 3N166
SYMBOL
LIMITS
CHARACTERISTIC
UNITS
CONDITIONS
MIN
MAX
Y
fs1
/Y
fs2
Forward Transconductance Ratio
0.90
1.0
ns
V
DS
= ‐15V, I
D
= ‐500µA , f = MHz
4
V
GS1‐2
Gate Source Threshold Voltage
‐‐
100
mV
V
DS
= ‐15V, I
D
= ‐500µA
Differential
∆V
GS1‐2
/∆T
Gate Source Threshold Voltage
‐‐
100
µV/°C
V
DS
= ‐15V, I
D
= ‐500µA
Differential Change with Temperature
T
A
= ‐55°C to = +25°C
SWITCHING TEST CIRCUIT
SWITCHING WAVEFORM & TEST CIRCUIT
Note 1 ‐ Absolute maximum ratings are limiting values above which 3N166 serviceability may be impaired. *
Note 2 – Per Transistor
Note 3 – Device must not be tested at ±125V more than once or longer than 300ms.
Note 4 – For design reference only, not 100% tested
Click To Buy
Output Admittance
‐‐
‐‐
300
Device Schematic
TO-78 (Bottom View)
Available Packages:
3N166 in TO-72
3N166 in bare die.
Please contact Micross for full
package and die dimensions
Tel: +44 1603 788967
Email:
chipcomponents@micross.com
Web:
http://www.micross.com/distribution
*To avoid possible damage to the device while wiring, testing, or in actual
operation, follow these procedures: To avoid the build‐up of static charge, the
leads of the devices should remain shorted together with a metal ring except
when being tested or used. Avoid unnecessary handling. Pick up devices by the
case instead of the leads. Do not insert or remove devices from circuits with the
power on, as transient voltages may cause permanant damage to the devices.
Information furnished by Linear Integrated Systems and Micross Components is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or
other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems.
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