CD-700-LAC-HEB-13.000 datasheet, PDF

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CD-700-LAC-HEB-13.000: DescriptionPhase Locked Loop, CQCC16, SMD-16; CategoryAnalog mixed-signal IC The signal circuit; File Size1MB，20 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com; Environmental Compliance

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CD-700-LAC-HEB-13.000 Overview

Phase Locked Loop, CQCC16, SMD-16

CD-700-LAC-HEB-13.000 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
package instruction	SMD-16
Reach Compliance Code	compliant
Analog Integrated Circuits - Other Types	PHASE LOCKED LOOP
JESD-30 code	R-CQCC-N16
JESD-609 code	e4
length	7.49 mm
Humidity sensitivity level	1
Number of functions	1
Number of terminals	16
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	QCCN
Encapsulate equivalent code	LCC16,.2X.3,40
Package shape	RECTANGULAR
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	2.13 mm
Maximum supply voltage (Vsup)	3.63 V
Minimum supply voltage (Vsup)	2.97 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
Temperature level	COMMERCIAL
Terminal surface	Gold (Au) - with Nickel (Ni) barrier
Terminal form	NO LEAD
Terminal pitch	1.02 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	40
width	5.08 mm

CD-700-LAC-HEB-13.000 Preview

CD-700

Flexible Modular Solution

A Quartz Stabilized PLL

I t ’s a phase-locked loop ASIC with a quartz stabilized VCXO!

Hermetic Seam Seal

16 Pad Leadless Chip Carrier

It will

•

Reduce: design time

component count

board space

•

Improve: jitter performance

reliability

Castallations For

Optimum board adhesion

Grounded Lid

It perf o rm s

•

Clock Recovery & Data Retiming

•

Frequency Translation

•

Clock Smoothing

•

Clock Switching

In applications up to 65.536 Mb/s:

•

ATM, SONET/SDH, DWDM

•

xDSL, Network Communications

•

Digital Audio/Video, PBX Systems

Vectron International 166 Glover Avenue, Norwalk, CT 06856-5160 Tel: 1-88-VECTRON-1 website: http://www.vectron.com

What Does It Do?

Vectron International's CD-700 is a user-configured, phase-locked loop (PLL) solution designed to simplify a wide variety of clock recovery and data retiming, frequency

translation, clock smoothing and clock switching applications. The device features a phase-lock loop ASIC with a quartz stabilized VCXO for superior stability and jitter

performance. This highly integrated module provides unsurpassed performance, reliability and quality. The proprietary ASIC device includes a refined Phase Detector, a Loop

Filter Op-Amp, a Loss of Signal Alarm with Clock Return to Nominal feature, a VCXO circuit, and an optional 2n divided output.

The ASIC and quartz resonator are housed in a hermetic 16-pad ceramic leadless chip carrier. The VCXO frequency (OUT1) and division factor (OUT2) are factory set in

accordance with customer specifications. PLL response is optimized for each application by the selection of external passive components. Software is available from Vectron

to aid in loop filter component selection and loop response modeling.

F e a t u re s :

PLL with quartz stabilized VCXO

Output jitter less than 20 ps

Loss of signal (LOS) alarm

Return to nominal clock upon LOS

Input data rates from 8 kb/s to 65.536 Mb/s

Surface mount option

Tri-state output

User defined PLL loop response

NRZ data compatible

Robust hermetic ceramic package

Single +5.0 V or +3.3V supply

Benefits:

Flexible modular solution

Reduce design time

Increase circuit reliability

Less board space

Reduces component count

What is the main

benefit of the

CD-700?

It’s a single drop-in

Quartz Stabilized

PLL solution.

W h a t’s Inside?

What Does It Do?

Pages 3-5

How Is It Used?

Pages 15-18

How Is It Built?

Pages 6-11

H o w I s It Packaged?

How Is It Ord e re d ?

Page 19

How Does It Perf o rm ?

Pages 12-14

Vectron International 166 Glover Avenue, Norwalk, CT 06856-5160 Tel: 1-88-VECTRON-1 website: http://www.vectron.com

Parameter

Output Frequency (ording option)

1,2

Out 1, 5.0 V option

Out 1, 3.3 V Option

For input RZ data, Manchester encoded data,

and input clock recovery applications, the

output clock must run at two times the input

rate to ensure that the input is clocked

correctly. Since the output clock has a max-

imum frequency of 65.536 MHz, these inputs

are limited to a maximum rate of 32.768 MHz.

OUT2 is a binary submultiple of OUT1, or

it may be disabled.

A 0.01uF and 0.1 parallel capacitor should be

located as close to pin 14 (and grounded) as

possible

Figure 1 defines these parameters. Figure 2

illustrates the equivalent five gate TTL load and

operating conditions under which these

parameters are tested and specified. Loads

greater than 15 pF will adversely effect rise/fall

time as well as symmetry.

A loss of signal (LOS) indicator is set to a

logic high if no transitions are detected at

DATAIN after 256 clock cycles. As soon

as a transition occurs at DATAIN, LOS is

set to a logic low.

Symmetry is defined as (ON TIME/PERIOD with

Vs=1.4 V for both 5.0 V and 3.3 V operation.

Symbol

Min

12.000

4.5

2.97

Typical

Max

65.537

51.840

Unit

MHz

Supply Voltage

+5.0

+3.3

Supply Current

5.0

3.3

5.5

3.63

Output Transition Times:

Rinse Time

Fall Time

Input Logic Levels:

Output Logic High

Output Logic Low

2.0

0.5

2.5

0.5

_ 75

ppm

Loss of Signal Indicator

Output Logic High

Output Logic Low

Output 1

Output 2

Symmetry or Duty Cycle

Out 1

Out 2

RCLK

Absolute Pull Range (ording option)

over operating temp, aging, power supply

variations

Test Conditions for APR (+5.0 V option)

Test Conditions for APR (+3.3 V option)

Gain Transfer

Phase Detector Gain

+5V option

+3.3V option

Operating temperature (ordering option)

Control Voltage Leakage Current

vcxo

0.53

0.35

0/70 or – 40/85

rad/V

Norminal Frequency on Loss of Signal

SYM1

SYM2

RCLK

APR

_ 50

_ 80

_100

0.5

0.3

Positive

40/60

45/55

40/60

4.5

3.0

Table 1.

Figure 1.

Vectron International 166 Glover Avenue, Norwalk, CT 06856-5160 Tel: 1-88-VECTRON-1 website: http://www.vectron.com

Figure 2.

Symbol

OPOUT

OPN

PHO

LOSIN

Function

Output terminal of internal operational amplifier.

Negative input terminal to internal operational amplifier.

Output signal produced by phase detector.

With LOSIN set to a logic high, the external input to the VCXO (VC) is

disabled and the VCXO returns to it’s nominal center frequency. With

LOSIN set to logic low, the external input to the VCXO is enabled. The

LOSIN input has an internal pull-down resistor.

DATAIN

CLKIN

GND

LOS

Input data stream to phase detector (TLL switching thresholds).

Input clock signal to phase detector (TTL switching thresholds).

Circuit and cover ground.

Loss of signal indicator is set to a logic high if no transitions are

detected at DATAIN after 256 clock cycles. As soon as a transition

occurs at DATAIN, LOS is set to a logic low .

TTL compatible recovered clock.

Divided version of internal VCXO output clock (TTL).

When set to a logic low, output pins OUT1, OUT2, RCLK, and RDATA

buffers are set to high-impedance state. When set to a logic high or

no connect, the device functions and output pins OUT1, OUT2, RCLK,

and RDATA are active. This input has an internal pull-up resistor.

Output clock of internal VCXO (TTL).

+5.0 V or +3.3 V

Positive input terminal to internal operational amplifier.

Control voltage input to internal voltage controlled crystal oscillator (VCXO).

RCLK

RDATA

OUT2

HIZ

Why would

someone buy

a CD-700?

To save design time,

reduce component

count, conserve

Table 2.

OUT1

VDD

OPP

board space,

and optimize

manufacturing

efficiency.

Figure 3.

Vectron International 166 Glover Avenue, Norwalk, CT 06856-5160 Tel: 1-88-VECTRON-1 website: http://www.vectron.com

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