SST49LF040B-33-4C-NHE datasheet, PDF

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SST49LF040B-33-4C-NHE: DescriptionFlash, 512KX8, 11ns, PQCC32, ROHS COMPLIANT, PLASTIC, MO-016AE, LCC-32; Categorystorage storage; File Size420KB，38 Pages; ManufacturerSST; Websitehttp://www.ssti.com; Environmental Compliance

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SST49LF040B-33-4C-NHE Overview

Flash, 512KX8, 11ns, PQCC32, ROHS COMPLIANT, PLASTIC, MO-016AE, LCC-32

SST49LF040B-33-4C-NHE Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Parts packaging code	QFJ
package instruction	QCCJ,
Contacts	32
Reach Compliance Code	unknown
ECCN code	EAR99
Maximum access time	11 ns
JESD-30 code	R-PQCC-J32
JESD-609 code	e3
length	13.97 mm
memory density	4194304 bit
Memory IC Type	FLASH
memory width	8
Number of functions	1
Number of terminals	32
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature
organize	512KX8
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Package shape	RECTANGULAR
Package form	CHIP CARRIER
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
Programming voltage	3 V
Certification status	Not Qualified
Maximum seat height	3.556 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL EXTENDED
Terminal surface	MATTE TIN
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	10
width	11.43 mm

SST49LF040B-33-4C-NHE Preview

4 Mbit LPC Flash

SST49LF040B

SST49LF040B4Mb LPC Flash memory

Advance Information

FEATURES:

• 4 Mbit SuperFlash Memory Array for Code or

Data Storage

– SST49LF040B: 512K x8 (4 Mbit)

• Conforms to Intel LPC Interface Specification

– Supports Single-Byte LPC Memory Cycle

• Flexible Erase Capability

– Uniform 4 KByte sectors

– Uniform 64 KByte overlay blocks

– Chip-Erase for PP Mode Only

• Single 3.0-3.6V Read and Write Operations

• Superior Reliability

– Endurance: 100,000 Cycles (typical)

– Greater than 100 years Data Retention

• Low Power Consumption

– Active Read Current: 6 mA (typical)

– Standby Current: 10 µA (typical)

• Fast Sector-Erase/Byte-Program Operation

– Sector-Erase Time: 18 ms (typical)

– Block-Erase Time: 18 ms (typical)

– Chip-Erase Time: 70 ms (typical)

– Byte-Program Time: 14 µs (typical)

– Chip Rewrite Time: 8 seconds (typical)

– Single-pulse Program or Erase

– Internal timing generation

• Two Operational Modes

– Low Pin Count (LPC) interface mode for

in-system operation

– Parallel Programming (PP) mode for fast

production programming

• LPC Interface Mode

– LPC bus interface supporting byte Read and

Write

– 33 MHz clock frequency operation

– WP# and TBL# pins provide hardware write

protection for entire chip and/or top Boot Block

– Block Locking Registers for individual block

Write-Lock and Lock-Down protection

– JEDEC Standard SDP Command Set

– Data# Polling and Toggle Bit for End-of-Write

detection

– 5 GPI pins for system design flexibility

– 4 ID pins for multi-chip selection

• Parallel Programming (PP) Mode

– 11-pin multiplexed address and 8-pin data

I/O interface

– Supports fast In-System or PROM programming

for manufacturing

• CMOS and PCI I/O Compatibility

• Packages Available

– 32-lead PLCC

– 32-lead TSOP (8mm x 14mm)

• All non-Pb (lead-free) devices are RoHS compliant

PRODUCT DESCRIPTION

The SST49LF040B flash memory devices are designed to

interface with host controllers (chipsets) that support a low-

pin-count (LPC) interface for BIOS code storage. Two inter-

face modes are supported by the SST49LF040B: LPC

Memory mode for in-system operation compatible with

Intel’s LPC Interface Specification and Parallel Program-

ming (PP) mode to interface with industry-standard pro-

gramming equipment.

The SST49LF040B flash memory devices are manufac-

tured with SST’s proprietary, high-performance SuperFlash

technology. The split-gate cell design and thick-oxide tun-

neling injector attain greater reliability and manufacturability

compared

with

alternative

approaches.

The

SST49LF040B devices significantly improve performance

and reliability, while lowering power consumption. The

SST49LF040B devices write (Program or Erase) with a

single 3.0-3.6V power supply.

The SST49LF040B use less energy during Erase and Pro-

gram than alternative flash memory technologies. The total

energy consumed is a function of the applied voltage, cur-

rent and time of application. Since for any given voltage

range the SuperFlash technology uses less current to pro-

gram and has a shorter erase time, the total energy con-

sumed during any Erase or Program operation is less than

alternative flash memory technologies.

The SuperFlash technology provides fixed Erase and Pro-

gram times, independent of the number of Erase/Program

cycles that have occurred. This means the system software

or hardware does not have to be calibrated or correlated to

the cumulative number of Erase cycles as is necessary

with alternative flash memory technologies, whose Erase

and Program times increase with accumulated Erase/Pro-

gram cycles.

S71226-03-000

5/06

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

Intel is a registered trademark of Intel Corporation.

These specifications are subject to change without notice.

4 Mbit LPC Flash

SST49LF040B

Advance Information

The SST49LF040B devices provide a maximum Byte-Pro-

gram time of 20 µsec. The entire memory can be erased

and programmed byte-by-byte typically in 8 seconds for the

SST49LF040B device, when using status detection fea-

tures such as Toggle Bit or Data# Polling to indicate the

completion of Program operation. To protect against inad-

vertent writes, the SST49LF040B device employ on-chip

hardware and software data protection (SDP) schemes. It

is offered with a typical endurance of 100,000 cycles. Data

retention is rated at greater than 100 years.

To meet high density, surface mount requirements, the

SST49LF040B devices are offered in 32-lead PLCC and a

32-lead TSOP package. In addition, SST is providing lead-

free (non-Pb) package options to address the growing

need for non-Pb solutions in electronic components. Non-

Pb package versions can be obtained by ordering products

with a package code suffix of “E” as the environmental

attribute in the product part number. See Figures 2 and 3

for pin assignments and Table 1 for pin descriptions.

TABLE OF CONTENTS

PRODUCT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

LIST OF FIGURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

LIST OF TABLES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

FUNCTIONAL BLOCKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Input/Output Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Input Communication Frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Interface Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Identification Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

General Purpose Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Write Protect / Top Block Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Row / Column Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Output Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Write Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

No Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

DEVICE MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

PRODUCT IDENTIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

MODE SELECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

LPC MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

LPC Memory Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

LPC Memory Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

S71226-03-000

5/06

4 Mbit LPC Flash

SST49LF040B

Advance Information

Abort Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Response to Invalid Fields for LPC Memory Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Multiple Device Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Write Operation Status Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

PARALLEL PROGRAMMING MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Write Operation Status Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Data Protection (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

SOFTWARE COMMAND SEQUENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

ELECTRICAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

AC Characteristics (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

AC Characteristics (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

PRODUCT ORDERING INFORMATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

PACKAGING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

S71226-03-000

5/06

4 Mbit LPC Flash

SST49LF040B

Advance Information

LIST OF FIGURES

FIGURE 1: Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

FIGURE 2: Pin Assignments for 32-lead PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

FIGURE 3: Pin Assignments for 32-lead TSOP (8mm x 14mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

FIGURE 4: Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

FIGURE 5: LPC Memory Read Cycle Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

FIGURE 6: LPC Memory Write Cycle Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

FIGURE 7: LCLK Waveform (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

FIGURE 8: Output Timing Parameters (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

FIGURE 9: Input Timing Parameters (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

FIGURE 10: Reset Timing Diagram (LPC MODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

FIGURE 11: Reset Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

FIGURE 12: Read Cycle Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

FIGURE 13: Write Cycle Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

FIGURE 14: Data# Polling Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

FIGURE 15: Toggle Bit Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

FIGURE 16: Byte-Program Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

FIGURE 17: Sector-Erase Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

FIGURE 18: Block-Erase Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

FIGURE 19: Chip-Erase Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

FIGURE 20: Software ID Entry and Read (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

FIGURE 21: Software ID Exit (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

FIGURE 22: AC Input/Output Reference Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

FIGURE 23: A Test Load Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

FIGURE 24: 32-lead Plastic Lead Chip Carrier (PLCC) SST Package Code: NH . . . . . . . . . . . . . . . . . . . . 36

FIGURE 25: 32-lead Thin Small Outline Package (TSOP) 8mm x 14mm SST Package Code: WH . . . . . . 37

S71226-03-000

5/06

4 Mbit LPC Flash

SST49LF040B

Advance Information

LIST OF TABLES

TABLE 1: Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

TABLE 2: Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

TABLE 3: LPC Memory Read Cycle Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

TABLE 4: LPC Memory Write Cycle Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

TABLE 5: LPC Memory Address Decoding Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

TABLE 6: LPC Memory Address bits definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

TABLE 7: LPC Memory Multiple Device Selection Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

TABLE 8: Block Locking Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

TABLE 9: Block Locking Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

TABLE 10: Operation Modes Selection (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

TABLE 11: Software Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

TABLE 12: DC Operating Characteristics (All Interfaces) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

TABLE 13: Recommended System Power-up Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

TABLE 14: Pin Capacitance (VDD=3.3V, TA=25 °C, f=1 Mhz, other pins open). . . . . . . . . . . . . . . . . . . . 22

TABLE 15: Reliability Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

TABLE 16: Clock Timing Parameters (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

TABLE 17: Read/Write Cycle Timing Parameters, V

=3.0-3.6V (LPC Mode) . . . . . . . . . . . . . . . . . . . . . 24

TABLE 18: AC Input/Output Specifications (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

TABLE 19: Interface Measurement Condition Parameters (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . 26

TABLE 20: Reset Timing Parameters, V

=3.0-3.6V (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

TABLE 21: Reset Timing Parameters, V

=3.0-3.6V (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

TABLE 22: Read Cycle Timing Parameters, V

=3.0-3.6V (PP Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . 28

TABLE 23: Program/Erase Cycle Timing Parameters, V

=3.0-3.6V (PP Mode) . . . . . . . . . . . . . . . . . . . 28

TABLE 24: Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

S71226-03-000

5/06

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SST49LF040B-33-4C-NHE Related Products

	SST49LF040B-33-4C-NHE
Description	Flash, 512KX8, 11ns, PQCC32, ROHS COMPLIANT, PLASTIC, MO-016AE, LCC-32
Is it Rohs certified?	conform to
Parts packaging code	QFJ
package instruction	QCCJ,
Contacts	32
Reach Compliance Code	unknown
ECCN code	EAR99
Maximum access time	11 ns
JESD-30 code	R-PQCC-J32
JESD-609 code	e3
length	13.97 mm
memory density	4194304 bit
Memory IC Type	FLASH
memory width	8
Number of functions	1
Number of terminals	32
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
organize	512KX8
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Package shape	RECTANGULAR
Package form	CHIP CARRIER
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
Programming voltage	3 V
Certification status	Not Qualified
Maximum seat height	3.556 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL EXTENDED
Terminal surface	MATTE TIN
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	10
width	11.43 mm

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