AD5323BRU-REEL datasheet, PDF - EEWORLD Datasheet

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AD5323BRU-REEL: DescriptionSERIAL INPUT LOADING, 8 us SETTLING TIME, 12-BIT DAC, PDSO16; Categorysemiconductor logic; File Size492KB，28 Pages; ManufacturerADI; Websitehttps://www.analog.com

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AD5323BRU-REEL Overview

SERIAL INPUT LOADING, 8 us SETTLING TIME, 12-BIT DAC, PDSO16

AD5323BRU-REEL Parametric

Parameter Name	Attribute value
Maximum linear error	0.1953 %
Number of functions	1
Number of terminals	16
Minimum operating temperature	-40 Cel
Maximum operating temperature	105 Cel
Processing package description	MO-153AB, TSSOP-16
each_compli	Yes
state	Active
Type of converter	D/A CONVERTER
Minimum analog output voltage	1.00E-3 V
Maximum analog output voltage	5.5 V
Input bit encoding	BINARY
Input format	SERIAL
jesd_30_code	R-PDSO-G16
jesd_609_code	e0
moisture_sensitivity_level	1
Number of digits	12
Packaging Materials	PLASTIC/EPOXY
ckage_code	TSSOP
ckage_equivalence_code	TSSOP16,.25
packaging shape	RECTANGULAR
Package Size	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
eak_reflow_temperature__cel_	240
wer_supplies__v_	2.5/5.5
qualification_status	COMMERCIAL
seated_height_max	1.2 mm
Rated settling time	8 µs
sub_category	Other Converters
Maximum supply voltage	0.4000 mA
Rated supply voltage	3 V
surface mount	YES
Craftsmanship	CMOS
Temperature level	INDUSTRIAL
terminal coating	TIN LEAD
Terminal form	GULL WING
Terminal spacing	0.6500 mm
Terminal location	DUAL
ime_peak_reflow_temperature_max__s_	30
length	5 mm
width	4.4 mm

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2.5 V to 5.5 V, 230 μA, Dual Rail-to-Rail

Voltage Output 8-/10-/12-Bit DACs

AD5303/AD5313/AD5323

FEATURES

AD5303: 2 buffered 8-bit DACs in 1 package

A version: ±1 LSB INL, B version: ±0.5 LSB INL

AD5313: 2 buffered 10-bit DACs in 1 package

A version: ±4 LSB INL, B version: ±2 LSB INL

AD5323: 2 buffered 12-bit DACs in 1 package

A version: ±16 LSB INL, B version: ±8 LSB INL

16-lead TSSOP package

Micropower operation: 300 μA @ 5 V (including reference

current)

Power-down to 200 nA @ 5 V, 50 nA @ 3 V

2.5 V to 5.5 V power supply

Double-buffered input logic

Guaranteed monotonic by design over all codes

Buffered/unbuffered reference input options

Output range: 0 V to V

REF

or 0 V to 2 V

REF

Power-on-reset to 0 V

SDO daisy-chaining option

Simultaneous update of DAC outputs via LDAC pin

Asynchronous CLR facility

Low power serial interface with Schmitt-triggered inputs

On-chip rail-to-rail output buffer amplifiers

GENERAL DESCRIPTION

The AD5303/AD5313/AD5323 are dual 8-/10-/12-bit buffered

voltage output DACs in a 16-lead TSSOP package that operate

from a single 2.5 V to 5.5 V supply, consuming 230 μA at 3 V.

Their on-chip output amplifiers allow the outputs to swing rail-to-

rail with a slew rate of 0.7 V/μs. The AD5303/AD5313/AD5323

utilize a versatile 3-wire serial interface that operates at clock

rates up to 30 MHz and is compatible with standard SPI, QSPI™,

MICROWIRE™, and DSP interface standards.

The references for the two DACs are derived from two reference

pins (one per DAC). These reference inputs may be configured

as buffered or unbuffered inputs. The parts incorporate a power-

on reset circuit, which ensures that the DAC outputs power up

to 0 V and remain there until a valid write to the device takes

place. There is also an asynchronous active low CLR pin that

clears both DACs to 0 V. The outputs of both DACs may be

updated simultaneously using the asynchronous LDAC input.

The parts contain a power-down feature that reduces the

current consumption of the devices to 200 nA at 5 V (50 nA

at 3 V) and provides software-selectable output loads while

in power-down mode. The parts may also be used in daisy-

chaining applications using the SDO pin.

The low power consumption of these parts in normal operation

makes them ideally suited to portable battery-operated equip-

ment. The power consumption is 1.5 mW at 5 V and 0.7 mW at

3 V, reducing to 1 μW in power-down mode.

APPLICATIONS

Portable battery-powered instruments

Digital gain and offset adjustment

Programmable voltage and current sources

Programmable attenuators

FUNCTIONAL BLOCK DIAGRAM

BUF A

REF

POWER-ON

RESET

INPUT

SYNC

SCLK

DIN

INPUT

SDO

DAC

STRING

DAC

INTERFACE

LOGIC

DAC

AD5303/AD5313/AD5323

STRING

DAC

BUFFER

OUT

POWER-DOWN

LOGIC

RESISTOR

NETWORK

BUFFER

OUT

GAIN-SELECT

LOGIC

RESISTOR

NETWORK

00472-001

DCEN

LDAC CLR

BUF B

REF

GND

Figure 1.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

AD5303/AD5313/AD5323

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

AC Characteristics........................................................................ 6

Timing Characteristics ................................................................ 6

Absolute Maximum Ratings............................................................ 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Terminology .................................................................................... 10

Typical Performance Characteristics ........................................... 11

Functional Description .................................................................. 15

Digital-to-Analog ....................................................................... 15

Resistor String ............................................................................. 15

DAC Reference Inputs ............................................................... 15

Output Amplifier........................................................................ 15

Power-On Reset .............................................................................. 16

Clear Function (CLR) ................................................................ 16

Serial Interface ................................................................................ 17

Input Shift Register .................................................................... 17

Low Power Serial Interface ....................................................... 17

Double-Buffered Interface ........................................................ 17

Power-Down Modes ...................................................................... 19

Microprocesser Interfacing ........................................................... 20

AD5303/AD5313/AD5323 to ADSP-2101 Interface............. 20

AD5303/AD5313/AD5323 to 68HC11/68L11 Interface ...... 20

AD5303/AD5313/AD5323 to 80C51/80L51 Interface.......... 20

AD5303/AD5313/AD5323 to MICROWIRE Interface ........ 20

Applications Information .............................................................. 21

Typical Application Circuit....................................................... 21

Bipolar Operation Using the AD5303/AD5313/AD5323..... 21

Opto-Isolated Interface for Process Control Applications ... 22

Decoding Multiple AD5303/AD5313/AD5323s.................... 22

AD5303/AD5313/AD5323 as a Digitally Programmable

Window Detector ....................................................................... 22

Coarse and Fine Adjustment Using the

AD5303/AD5313/AD5323 ....................................................... 23

Daisy-Chain Mode ..................................................................... 23

Power Supply Bypassing and Grounding................................ 24

Outline Dimensions ....................................................................... 25

Ordering Guide .......................................................................... 25

REVISION HISTORY

6/07—Rev. A to Rev. B

Updated Format..................................................................Universal

Changes to Table 4............................................................................ 8

Changes to the Ordering Guide.................................................... 25

8/03—Rev. 0 to Rev. A

Added A Version.................................................................Universal

Changes to Features.......................................................................... 1

Changes to Specifications ................................................................ 2

Changes to Absolute Maximum Ratings ....................................... 5

Changes to Ordering Guide ............................................................ 5

Updated Outline Dimensions ....................................................... 18

4/99—Revision 0: Initial Version

Rev. B | Page 2 of 28

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