AD9129 datasheet, PDF - EEWORLD Datasheet

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AD9129: DescriptionPARALLEL, WORD INPUT LOADING, 0.013 us SETTLING TIME, 11-BIT DAC, PBGA160; Categorysemiconductor logic; File Size3MB，68 Pages; ManufacturerADI; Websitehttps://www.analog.com

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AD9129 Overview

PARALLEL, WORD INPUT LOADING, 0.013 us SETTLING TIME, 11-BIT DAC, PBGA160

AD9129 Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	160
Maximum operating temperature	85 Cel
Minimum operating temperature	-40 Cel
Rated supply voltage	1.8 V
Processing package description	ROHS COMPLIANT, MO-205AE, CSPBGA-160
state	ACTIVE
Craftsmanship	CMOS
packaging shape	SQUARE
Package Size	GRID ARRAY, LOW PROFILE, FINE PITCH
surface mount	Yes
Terminal form	BALL
Terminal spacing	0.8000 mm
Terminal location	BOTTOM
Packaging Materials	PLASTIC/EPOXY
Temperature level	INDUSTRIAL
Rated negative supply voltage	-1.5 V
Input format	PARALLEL, WORD
Type of converter	11-BIT DAC
Input bit encoding	BINARY
Rated settling time	0.0130 us
Maximum analog output voltage	2.5 V
Minimum analog output voltage	1.5 V

User Manual

【User Guides】DC932A - Demo Manual

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11/14½、5.7GSPS、

RF数模½换器

AD9119/AD9129

特性

DAC更新速率：最高达5.7 GSPS

直接RF频率合成(2.85

GSPS数据速率)

直流至1.425

GHz(基带模式)

直流至1.0

GHz(2倍插值模式)

1.425 GHz至4.2 GHz(混合模式)

可旁路的2倍插值

出色的动态性½

支持DOCSIS

3.0½带ACLR/谐波性½

8个QAM½½波：ACLR > 65 dBc

业界领先的单/多½½波IF或RF频率合成

4½½波W-CDMA ACLR (2457.6 MSPS)

OUT

= 900 MHz，ACLR = 71 dBc(基带模式)

OUT

= 2100 MHz，ACLR = 68 dBc(混合模式)

OUT

= 2700 MHz，ACLR = 67 dBc(混合模式)

双端口LVDS和DHSTL数据接口

工½速率最高达1.425

GSPS

源同步DDR时钟，带奇偶校验½

½功耗：1.0

W(2.85 GSPS)；1.3 W(5.7 GSPS)

RESET

功½框图

IRQ

I250U VREF

AD9129

SDIO

SDO

SCLK

FRM_x

(FRAME/

PARITY)

P0_D[13:0]P,

P0_D[13:0]N

DLL

DCI_x

1.2V

SPI

LVDS DDR

RECEIVER

MIX-

NORMAL MODE

DATA ASSEMBLER

BASEBAND

MODE

DATA

LATCH

4× FIFO

Tx DAC

CORE

IOUTP

IOUTN

2×

P1_D[13:0]P,

P1_D[13:0]N

LVDS DDR

RECEIVER

PLL

DCO_x

CLOCK

DISTRIBUTION

DCR

11149-001

DACCLK_x

应用

½带通信系统

CMTS/VOD

无线基础设½：W-CDMA、LTE、点对点

仪器仪表、自动测试设备(ATE)

雷达、干扰发射器

图1.

概述

AD9119/AD9129是高性½11½/14½RF数模½换器(DAC)，

支持最高达2.85

GSPS的数据速率。DAC内核基于一个四通道

开关结构，½双边沿时钟½够有效运行，配½为混频模式

(Mix-Mode™)或2倍插值时，½将DAC更新速率提高至5.7 GSPS。

它的高动态范围和½带½特性可产生高达4.2

GHz的多½½波。

在基带模式下，元件的½带½½力和高动态范围相结合，

在CATV基础设½应用中可支持1至158个连续½½波。还可

以选择两个可选2倍插值滤波器，通过将DAC更新速率提

高两倍来简化后重建构滤波器。在混频模式中，AD9119/

AD9129可在二阶和三阶奈奎斯特区内重构RF½½波，同时

仍保持高达4.2

GHz的出色动态范围。其高性½NMOS DAC

内核具有四通道开关结构，½以最小输出功耗实现业界领

先的直接RF频率合成性½。输出电流可以在9.5

mA至34.4 mA

范围内进行编程。

AD9119/AD9129包含数项功½，½进一步简化系统集成。

双端口源同步LVDS接口简化了与主机FPGA/ASIC的数据接

口。它还包含了差分帧/奇偶校验½来监控接口的完整性。

片内延迟锁环(DLL)用于优化不同时钟域之间的时序。

串行外设接口(SPI)用于配½AD9119/AD9129和监控回读寄

存器的状态。AD9119/AD9129采用0.18

m CMOS工艺制造，

以+1.8

V和-1.5 V电源供电。该器件提供160引脚芯片级球栅

阵列封装。

产品特色

高动态范围和信号重建带½支持高达4.2

GHz的RF信号

频率合成。

具有双端口接口和双倍数据速率(DDR)

LVDS数据接收机，

支持2850

MSPS的最大½换速率。

采用CMOS工艺制造，并利用专有开关技术来增强动态

性½。

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Speci cations subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

Document Feedback

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

ADI中文版数据手册是英文版数据手册的译文，敬请谅解翻译中可½存在的语言组织或翻译错误，ADI不对翻译中存在的差异或由此产生的错误负责。如需确认任½词语的准确性，请参考ADI提供

的最新英文版数据手册。

AD9119/AD9129

目½

特性..................................................................................................

应用..................................................................................................

功½框图

......................................................................................... 1

概述..................................................................................................

产品特色

......................................................................................... 1

修订历史

......................................................................................... 2

技术规格

......................................................................................... 3

直流规格....................................................................................

LVDS数字规格 ......................................................................... 4

HSTL数字规格 ......................................................................... 4

串行端口和CMOS引脚规格..................................................

交流规格....................................................................................

绝对最大额定值............................................................................

热阻

............................................................................................ 7

ESD警告..................................................................................... 7

引脚配½和功½描述

................................................................... 8

典型性½参数

.............................................................................. 12

AD9119..................................................................................... 12

AD9129..................................................................................... 22

术语................................................................................................

串行通信端口概述

..................................................................... 36

串行外设接口(SPI)

................................................................ 36

SPI通用操½............................................................................ 36

指令模式(8½指令)

............................................................... 36

串行外设接口引脚描述

....................................................... 36

MSB/LSB传输.......................................................................... 37

串行端口配½

......................................................................... 37

工½原理

....................................................................................... 38

LVDS数据端口接口............................................................... 39

数字数据路径描述

................................................................ 42

中断请求..................................................................................

接口时序验证

.............................................................................. 48

采样错误检测(SED)操½

..................................................... 48

SED示例................................................................................... 48

模拟接口考虑

.............................................................................. 49

模拟工½模式

......................................................................... 49

时钟输入..................................................................................

PLL ............................................................................................ 50

基准电压源

............................................................................. 51

模拟输出..................................................................................

启动序列..................................................................................

器件配½寄存器..........................................................................

器件配½寄存器映射............................................................

器件配½寄存器描述............................................................

外½尺寸

....................................................................................... 66

订购指南..................................................................................

修订历史

2013年9月—修订版0至修订版A

更改产品名称

................................................................................ 1

更改特性和概述部分

................................................................... 1

更改表1

........................................................................................... 3

更改表2和表3

................................................................................ 4

更改表5的动态性½参数.............................................................

更改图10和图13

.......................................................................... 13

更改图21和图23

.......................................................................... 15

更改图24和图27

.......................................................................... 16

更改图35和图37

.......................................................................... 18

更改图62、图65和图67

............................................................. 23

更改图76和图79

.......................................................................... 25

更改图84、图85和图87

............................................................. 27

更改图90和图92

.......................................................................... 28

更改图95和图97

.......................................................................... 29

更改图118

..................................................................................... 33

更改串行通信端口概述部分....................................................

更改工½原理部分

..................................................................... 38

更改LVDS数据端口接口部分

.................................................. 39

更改多DAC同步部分.................................................................

更改PLL部分................................................................................

更改基准电压源部分

................................................................. 51

更改表16的寄存器0x01

............................................................. 54

更改表17

....................................................................................... 55

更改表37的½6

............................................................................ 61

更改表49、表50、表51和表52

................................................ 63

更改表53、表54、表55、表56

和表57............................................................................................

2013年1月—修订版0：初始版

Rev. A | Page 2 of 68

AD9129 Related Products

	AD9129	AD9119
Description	PARALLEL, WORD INPUT LOADING, 0.013 us SETTLING TIME, 11-BIT DAC, PBGA160	PARALLEL, WORD INPUT LOADING, 0.013 us SETTLING TIME, 11-BIT DAC, PBGA160
Number of functions	1	1
Number of terminals	160	160
Maximum operating temperature	85 Cel	85 Cel
Minimum operating temperature	-40 Cel	-40 Cel
Rated supply voltage	1.8 V	1.8 V
Processing package description	ROHS COMPLIANT, MO-205AE, CSPBGA-160	ROHS COMPLIANT, MO-205AE, CSPBGA-160
state	ACTIVE	ACTIVE
Craftsmanship	CMOS	CMOS
packaging shape	SQUARE	SQUARE
Package Size	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH
surface mount	Yes	Yes
Terminal form	BALL	BALL
Terminal spacing	0.8000 mm	0.8000 mm
Terminal location	BOTTOM	BOTTOM
Packaging Materials	PLASTIC/EPOXY	PLASTIC/EPOXY
Temperature level	INDUSTRIAL	INDUSTRIAL
Rated negative supply voltage	-1.5 V	-1.5 V
Input format	PARALLEL, WORD	PARALLEL, WORD
Type of converter	11-BIT DAC	11-BIT DAC
Input bit encoding	BINARY	BINARY
Rated settling time	0.0130 us	0.0130 us
Maximum analog output voltage	2.5 V	2.5 V
Minimum analog output voltage	1.5 V	1.5 V

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