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Structure
Product
Type
Feature
Silicon monolithic Integrated circuit
Clock Generator
BU3056FV
To generate clocks for BD-player, BD-recorder system
Selection of PDB pin enabling Power-Down function
○Absolute
Maximum Ratings
Symbol
Ratings
Unit
Parameter
Supply voltage
VDD
V
-0.3
½
4.0
Input Voltage
VIN
V
-0.3
½
VDD+0.3
Storage Temperature range
Tstg
℃
-55
½
125
※
1
Power dissipation
PD
mW
450
※
1
A measure value at mounting on 70mm
×
70mm
×
1.6mm glass epoxy substrate.
In the case of exceeding Ta=25
℃
, 4.5mW should be reduced per 1
℃
.
※
The radiation-resistance design is not carried out.
※
Operation is not guaranteed.
○Operating
Conditions
Parameter
Supply voltage
Input ”H” Voltage
Input ”L” Voltage
Operating Temperature
Output load
Symbol
VDD
VIH
VIL
Topr
CL
Ratings
3.0
½
3.6
0.8VDD
½
VDD
0.0
½
0.2VDD
-20
½
85
15 (MAX)
Unit
V
V
V
℃
pF
Status of this document
The Japanese version of this document is the formal specification.
A customer may use this translation version only for a reference to help reading the formal version.
If there are any differences in translation version of this document, formal version takes priority.
REV. A
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○
Electrical Characteristics
（
VDD=3.3V,Ta=25
℃
,at No Load ,unless otherwise specified
）
Parameter
Pull-up load
Pull-down load
Output H voltage
Output L voltage
Consumption
current1
Consumption
current2
Consumption
current3
Consumption
current4
Symbol
Min.
Rpu
Rpd
VOH
VOL
IDD1
IDD2
IDD3
IDD4
28
25
2.9
－
－
－
－
－
Limit
Typ.
59
53
－
－
16
25
22
13
Max.
90
80
－
0.4
21
33
29
17
kΩ
kΩ
V
V
mA
mA
mA
mA
Input PIN pull-up load value
Input PIN pull-down load value
IOH=
－
4.0mA
IOL=4.0mA
MODE1=L, MODE2=L,
Xtal=12.000MHz
MODE1=L, MODE2=H,
Xtal=12.000MHz
MODE1=H, MODE2=L,
Xtal=24.576MHz
MODE1=H, MODE2=H,
Xtal=25.000MHz
Unit
Conditions
○
Block Diagram
CLK0
XIN
PLL1
XOUT
CLK1
PLL2
CLK2
PDB
MODE1
MODE2
Logic
○
Output Frequency
MODE1
L
MODE2
L
PDB
L
H
L
H
L
H
L
H
L
H
H
H
Input Frequency
12.0000MHz
12.0000MHz
12.0000MHz
12.0000MHz
24.5760MHz
24.5760MHz
25.0000MHz
25.0000MHz
CLK0
L Output
12.0000MHz
L Output
12.0000MHz
L Output
24.5760MHz
L Output
25.0000MHz
CLK1
L Output
33.3333MHz
L Output
60.0000MHz
L Output
25.0000MHz
L Output
25.0000MHz
CLK2
L Output
27.0000MHz
L Output
48.0000MHz
L Output
48.0000MHz
L Output
25.0000MHz
L
H
REV. A
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○Package
Outline, Appearance of Marker
3056F
Lot No.
SSOP-B16
○Pin
Function
PIN
No.
1
2
3
4
5
6
7
8
PIN Name
VDD0
VSS0
CLK0
AVDD
AVSS
XIN
XOUT
TEST
Function
Power supply for CLK0 output
GND for CLK0 output
CLK0 output terminal
Analog power supply
Analog GND
Crystal input terminal
Crystal output terminal
TEST terminal is normally OPEN
With pull-down resister
PIN
No.
9
10
11
12
13
14
15
16
PIN Name
MODE2
MODE1
CLK1
VSS
VDD
CLK2
PDB
TEST_B
Function
MODE control terminal 2
( CMOS Input )
MODE control terminal 1
( CMOS Input )
CLK1 output terminal
Logic GND
Logic power supply
CLK2 output terminal
Power-Down control terminal
With pull-up resister
TEST terminal is normally OPEN
With pull-down resister
●Cautions
on use（BU3056FV）
·BU3056FV must be basically mounted on the board. (If it is not circuit board mounting, it can't sometimes get a
character fully.)
·Capacitors 0.1uF need to be placed between 1PIN(VDD0) and 2PIN(VSS0), 4PIN(AVDD) and 5PIN(AVSS),
13PIN(VDD) and 12PIN(VSS).
·It is effective as an EMI countermeasure when the capacitor (less than 1Ω) which puts ferrite beads in the
starting point of the power supply supplied to the BU3056FV by a circuit board and which makes the power
supply-GND space have a requested high frequency as to the bypass is inserted.
·For ICs with more than one power supply, it is possible that rush current may flow instantaneously due to the internal
powering sequence and delays. Therefore, give special consideration to power coupling capacitance, power wiring,
width of ground wiring, and routing of wiring.
REV. A
4/4
●
Cautions on use（common）
（１）Absolute
Maximum Ratings
An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down
devices, thus making impossible to identify breaking mode such as a short circuit or an open circuit. If any special mode exceeding the
absolute maximum ratings is assumed, consideration should be given to take physical safety measures including the use of fuses, etc.
（２）Operating
conditions
These conditions represent a range within which characteristics can be provided approximately as expected. The electrical characteristics
are guaranteed under the conditions of each parameter.
（３）Reverse
connection of power supply connector
The reverse connection of power supply connector can break down ICs. Take protective measures against the breakdown due to the
reverse connection, such as mounting an external diode between the power supply and the IC’s power supply terminal.
（４）Power
supply line
Design PCB pattern to provide low impedance for the wiring between the power supply and the GND lines.In this regard, for the digital block
power supply and the analog block power supply, even though these power supplies has the same level of potential, separate the power
supply pattern for the digital block from that for the analog block, thus suppressing the diffraction of digital noises to the analog block power
supply resulting from impedance common to the wiring patterns. For the GND line, give consideration to design the patterns in a similar
manner.
Furthermore, for all power supply terminals to ICs, mount a capacitor between the power supply and the GND terminal. At the same time, in
order to use an electrolytic capacitor, thoroughly check to be sure the characteristics of the capacitor to be used present no problem
including the occurrence of capacity dropout at a low temperature, thus determining the constant.
（５）GND
voltage
Make setting of the potential of the GND terminal so that it will be maintained at the minimum in any operating state. Furthermore, check to
be sure no terminals are at a potential lower than the GND voltage including an actual electric transient.
（６）Short
circuit between terminals and erroneous mounting
In order to mount ICs on a set PCB, pay thorough attention to the direction and offset of the ICs. Erroneous mounting can break down the
ICs. Furthermore, if a short circuit occurs due to foreign matters entering between terminals or between the terminal and the power supply
or the GND terminal, the ICs can break down.
（７）Operation
in strong electromagnetic field
Be noted that using ICs in the strong electromagnetic field can malfunction them.
（８）Inspection
with set PCB
On the inspection with the set PCB, if a capacitor is connected to a low-impedance IC terminal, the IC can suffer stress. Therefore, be sure
to discharge from the set PCB by each process. Furthermore, in order to mount or dismount the set PCB to/from the jig for the inspection
process, be sure to turn OFF the power supply and then mount the set PCB to the jig. After the completion of the inspection, be sure to turn
OFF the power supply and then dismount it from the jig. In addition, for protection against static electricity, establish a ground for the
assembly process and pay thorough attention to the transportation and the storage of the set PCB.
（９）Input
terminals
In terms of the construction of IC, parasitic elements are inevitably formed in relation to potential. The operation of the parasitic element can
cause interference with circuit operation, thus resulting in a malfunction and then breakdown of the input terminal. Therefore, pay thorough
attention not to handle the input terminals, such as to apply to the input terminals a voltage lower than the GND respectively, so that any
parasitic element will operate. Furthermore, do not apply a voltage to the input terminals when no power supply voltage is applied to the IC.
In addition, even if the power supply voltage is applied, apply to the input terminals a voltage lower than the power supply voltage or within
the guaranteed value of electrical characteristics.
（１０）Ground
wiring pattern
If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND pattern from the
small-signal GND pattern and establish a single ground at the reference point of the set PCB so that resistance to the wiring pattern and
voltage fluctuations due to a large current will cause no fluctuations in voltages of the small-signal GND. Pay attention not to cause
fluctuations in the GND wiring pattern of external parts as well.
（１１）External
capacitor
In order to use a ceramic capacitor as the external capacitor, determine the constant with consideration given to a degradation in the
nominal capacitance due to DC bias and changes in the capacitance due to temperature, etc.
REV. A
Notice
Notes
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