Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
CONTENTS
1
1.1
1.2
1.3
1.4
2
3
4
5
6
7
8
8.1
8.2
8.3
8.4
8.5
9
9.1
9.2
9.3
9.4
9.5
9.6
10
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
10.10
10.11
FEATURES
General
Control
IEC 60958 input
Digital sound processing and DAC
APPLICATIONS
GENERAL DESCRIPTION
ORDERING INFORMATION
QUICK REFERENCE DATA
BLOCK DIAGRAM
PINNING
FUNCTIONAL DESCRIPTION
Clock regeneration and lock detection
Mute
Auto mute
Data path
Control
L3-BUS DESCRIPTION
General
Device addressing
Register addressing
Data write mode
Data read mode
Initialization string
I
2
C-BUS
DESCRIPTION
19.2
19.3
19.4
19.5
20
21
22
23
Characteristics of the I
2
C-bus
Bit transfer
Byte transfer
Data transfer
Start and stop conditions
Acknowledgment
Device address
Register address
Write and read data
Write cycle
Read cycle
11
11.1
11.2
11.3
11.4
12
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
12.9
12.10
12.11
13
14
15
16
17
18
19
19.1
UDA1352TS
SPDIF SIGNAL FORMAT
SPDIF channel encoding
SPDIF hierarchical layers for audio data
SPDIF hierarchical layers for digital data
Timing characteristics
REGISTER MAPPING
SPDIF mute setting (write)
Power-down settings (write)
Volume control left and right (write)
Sound feature mode, treble and bass boost
settings (write)
Mute (write)
Polarity (write)
SPDIF input settings (write)
Interpolator status (read-out)
SPDIF status (read-out)
Channel status (read-out)
FPLL status (read-out)
LIMITING VALUES
THERMAL CHARACTERISTICS
CHARACTERISTICS
TIMING CHARACTERISTICS
APPLICATION INFORMATION
PACKAGE OUTLINE
SOLDERING
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
Suitability of surface mount IC packages for
wave and reflow soldering methods
DATA SHEET STATUS
DEFINITIONS
DISCLAIMERS
PURCHASE OF PHILIPS I
2
C COMPONENTS
2002 Nov 22
2
Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
1
1.1
FEATURES
General
UDA1352TS
•
2.7 to 3.6 V power supply
•
Integrated digital filter and Digital-to-Analog
Converter (DAC)
•
256f
s
system clock output
•
20-bit data path in interpolator
•
High performance
•
No analog post filtering required for DAC
•
Supporting sampling frequencies from 28 up to 55 kHz.
1.2
Control
•
Bass boost and treble control in L3-bus or I
2
C-bus mode
•
Interpolating filter (f
s
to 64f
s
) by means of a cascade of
a recursive filter and a FIR filter
•
Fifth-order noise shaper (operating at 64f
s
) generates
the bitstream for the DAC
•
Filter Stream DAC (FSDAC).
2
APPLICATIONS
•
Controlled either by means of static pins, I
2
C-bus or
L3-bus microcontroller interface.
1.3
IEC 60958 input
•
Digital audio systems.
3
GENERAL DESCRIPTION
•
On-chip amplifier for converting IEC 60958 input to
CMOS levels
•
Lock indication signal available on pin LOCK
•
Information of the Pulse Code Modulation (PCM) status
bit and the non-PCM data detection is available on
pin PCMDET
•
For left and right 40 key channel-status bits available via
L3-bus or I
2
C-bus interface.
1.4
Digital sound processing and DAC
The UDA1352TS is a single-chip IEC 60958 audio
decoder with an integrated stereo DAC employing
bitstream conversion techniques.
A lock indication signal is available on pin LOCK,
indicating that the IEC 60958 decoder is locked.
A separate pin PCMDET is available to indicate whether
or not the PCM data is applied to the input.
By default, the DAC output is muted when the decoder is
out-of-lock. However, this setting can be overruled in the
L3-bus or I
2
C-bus mode.
The UDA1352TS has IEC 60958 input to the DAC only
and is in SSOP28 package.
Besides the UDA1352TS, the UDA1352HL is also
available. The UDA1352HL is the full featured version in
LQFP48 package.
•
Automatic de-emphasis when using IEC 60958 input
with 32.0, 44.1 and 48.0 kHz audio sample frequencies
•
Soft mute by means of a cosine roll-off circuit selectable
via pin MUTE, L3-bus or I
2
C-bus interface
•
Left and right independent dB linear volume control with
0.25 dB steps from 0 to
−50
dB, 1 dB steps to
−60,
−66
and
−∞
dB
4
ORDERING INFORMATION
TYPE
NUMBER
PACKAGE
NAME
SSOP28
DESCRIPTION
plastic shrink small outline package; 28 leads; body width 5.3 mm
VERSION
SOT341-1
UDA1352TS
2002 Nov 22
3
Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
UDA1352TS
5 QUICK REFERENCE DATA
V
DDD
= V
DDA
= 3.0 V; IEC 60958 input with f
s
= 48.0 kHz; T
amb
= 25
°C;
R
L
= 5 kΩ; all voltages measured with respect
to ground; unless otherwise specified.
SYMBOL
Supplies
V
DDD
V
DDA
I
DDA(DAC)
I
DDA(PLL)
I
DDD(C)
I
DDD
P
General
t
rst
T
amb
V
o(rms)
∆V
o
(THD+N)/S
reset active time
ambient temperature
−
−40
f
i
= 1.0 kHz tone at 0 dBFS; note 1
f
i
= 1.0 kHz tone
f
i
= 1.0 kHz tone
at 0 dBFS
at
−40
dBFS; A-weighted
f
i
= 1.0 kHz tone
−
−
−
−82
−60
100
110
−77
−52
−
−
dB
dB
dB
dB
850
−
250
−
900
0.1
−
+85
µs
°C
mV
dB
digital supply voltage
analog supply voltage
analog supply current of DAC
analog supply current of PLL
digital supply current of core
digital supply current
power dissipation
DAC in playback mode
DAC in Power-down mode
power-on
power-down; clock off
2.7
2.7
−
−
−
−
−
−
−
3.0
3.0
3.3
35
0.3
9
0.3
38
tbf
3.6
3.6
−
−
−
−
−
−
−
V
V
mA
µA
mA
mA
mA
mW
mW
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Digital-to-analog converter
output voltage (RMS value)
unbalance of output voltages
total harmonic
distortion-plus-noise to signal
ratio
signal-to-noise ratio
channel separation
950
0.4
S/N
α
cs
Note
f
i
= 1.0 kHz tone; code = 0; A-weighted 95
1. The output voltage of the DAC is proportional to the DAC power supply voltage.
2002 Nov 22
4
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