FM24C04B
4Kb Serial 5V F-RAM Memory
Features
4K bit Ferroelectric Nonvolatile RAM
Organized as 512 x 8 bits
High Endurance 10
12
Read/Writes
38 Year Data Retention
NoDelay™ Writes
Advanced High-Reliability Ferroelectric Process
Fast Two-wire Serial Interface
Up to 1 MHz maximum bus frequency
Direct hardware replacement for EEPROM
Supports legacy timing for 100 kHz & 400 kHz
Low Power Operation
5V operation
100
A
Active Current (100 kHz)
4
A
(typ.) Standby Current
Industry Standard Configuration
Industrial Temperature -40 C to +85 C
8-pin “Green”/RoHS SOIC (-G)
Description
The FM24C04B is a 4-kilobit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or FRAM is
nonvolatile and performs reads and writes like a
RAM. It provides reliable data retention for 38 years
while eliminating the complexities, overhead, and
system level reliability problems caused by EEPROM
and other nonvolatile memories.
The FM24C04B performs write operations at bus
speed. No write delays are incurred. Data is written to
the memory array in the cycle after it has been
successfully transferred to the device. The next bus
cycle may commence immediately without the need
for data polling. The FM24C04B is capable of
supporting 10
12
read/write cycles, or a million times
more write cycles than EEPROM.
These capabilities make the FM24C04B ideal for
nonvolatile memory applications requiring frequent
or rapid writes. Examples range from data collection
where the number of write cycles may be critical, to
demanding industrial controls where the long write
time of EEPROM can cause data loss. The
combination of features allows more frequent data
writing with less overhead for the system.
The FM24C04B provides substantial benefits to users
of serial EEPROM, yet these benefits are available in
a hardware drop-in replacement. The FM24C04B is
available in an industry standard 8-pin SOIC package
and uses a familiar two-wire protocol. The
specifications are guaranteed over the industrial
temperature range from -40°C to +85°C.
Pin Configuration
NC
A1
A2
VSS
1
2
3
4
8
7
6
5
VDD
WP
SCL
SDA
Pin Names
A1-A2
SDA
SCL
WP
VSS
VDD
Function
Device Select Address 1 and 2
Serial Data/Address
Serial Clock
Write Protect
Ground
Supply Voltage
Ordering Information
FM24C04B-G
FM24C04B-GTR
“Green”/RoHS 8-pin SOIC
“Green”/RoHS 8-pin SOIC,
Tape & Reel
This product conforms to specifications per the terms of the Ramtron
standard warranty. The product has completed Ramtron’s internal
qualification testing and has reached production status.
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
Rev. 3.0
Jan. 2012
www.ramtron.com
Page 1 of 12
FM24C04B
Counter
Address
Latch
64 x 64
FRAM Array
8
SDA
Serial to Parallel
Converter
Data Latch
SCL
WP
A1
A2
Control Logic
Figure 1. Block Diagram
Pin Description
Pin Name
A1-A2
I/O
Input
Pin Description
Address 1-2: The address pins set the device select address. The device address value
in the 2-wire slave address must match the setting of these two pins. These pins are
internally pulled down.
Serial Data/Address: This is a bi-directional pin used to shift serial data and addresses
for the two-wire interface. It employs an open-drain output and is intended to be wire-
OR’d with other devices on the two-wire bus. The input buffer incorporates a Schmitt
trigger for noise immunity and the output driver includes slope control for falling
edges. A pull-up resistor is required.
Serial Clock: The serial clock input for the two-wire interface. Data is clocked out of
the device on the SCL falling edge, and clocked in on the SCL rising edge. The SCL
input also incorporates a Schmitt trigger input for improved noise immunity.
Write Protect: When WP is high, the entire array is write-protected. When WP is low,
all addresses may be written. This pin is internally pulled down.
No connect
Supply Voltage
Ground
SDA
I/O
SCL
Input
WP
NC
VDD
VSS
Input
-
Supply
Supply
Rev. 3.0
Jan. 2012
Page 2 of 12
FM24C04B
Overview
The FM24C04B is a serial FRAM memory. The
memory array is logically organized as 512 x 8 and is
accessed using an industry standard two-wire
interface. Functional operation of the FRAM is
similar to serial EEPROMs. The major difference
between the FM24C04B and a serial EEPROM with
the same pinout relates to its superior write
performance.
Two-wire Interface
The FM24C04B employs a bi-directional two-wire
bus protocol using few pins and little board space.
Figure 2 illustrates a typical system configuration
using the FM24C04B in a microcontroller-based
system. The industry standard two-wire bus is
familiar to many users but is described in this section.
By convention, any device that is sending data onto
the bus is the transmitter while the target device for
this data is the receiver. The device that is controlling
the bus is the master. The master is responsible for
generating the clock signal for all operations. Any
device on the bus that is being controlled is a slave.
The FM24C04B is always a slave device.
The bus protocol is controlled by transition states in
the SDA and SCL signals. There are four conditions:
Start, Stop, Data bit, and Acknowledge. Figure 3
illustrates the signal conditions that specify the four
states. Detailed timing diagrams are shown in the
electrical specifications.
Memory Architecture
When accessing the FM24C04B, the user addresses
512 locations each with 8 data bits. These data bits
are shifted serially. The 512 addresses are accessed
using the two-wire protocol, which includes a slave
address (to distinguish other devices), a page address,
and a word address. The word address consists of 8-
bits that specify one of 256 addresses. The page
address is 1-bit and so there are 2 pages of 256
locations. The complete address of 9-bits specifies
each byte address uniquely.
Most functions of the FM24C04B either are
controlled by the two-wire interface or are handled
automatically by on-board circuitry. The memory is
read or written at the speed of the two-wire bus.
Unlike an EEPROM, it is not necessary to poll the
device for a ready condition since writes occur at bus
speed. That is, by the time a new bus transaction can
be shifted into the part, a write operation will be
complete. This is explained in more detail in the
interface section below.
Users can expect several obvious system benefits
from the FM24C04B due to its fast write cycle and
high endurance as compared with EEPROM.
However there are less obvious benefits as well. For
example in a high noise environment, the fast-write
operation is less susceptible to corruption than an
EEPROM since it is completed quickly. By contrast
an EEPROM requiring milliseconds to write is
vulnerable to noise during much of the cycle.
Note that the FM24C04B contains no power
management circuits other than a simple internal
power-on reset. It is the user’s responsibility to ensure
that V
DD
is within data sheet tolerances to prevent
incorrect operation.
VDD
Microcontroller
Rmin = 1.8 Kohm
Rmax = tR/Cbus
SDA
SCL
SDA
SCL
VDD
FM24C04B
A1 A2
FM24C04B
A1 A2
Figure 2. Typical System Configuration
Rev. 3.0
Jan. 2012
Page 3 of 12
FM24C04B
Figure 3. Data Transfer Protocol
Stop Condition
A Stop condition is indicated when the bus master
drives SDA from low to high while the SCL signal is
high. All operations must end with a Stop condition. If
an operation is pending when a stop is asserted, the
operation will be aborted. The master must have
control of SDA (not a memory read) in order to assert
a Stop condition.
Start Condition
A Start condition is indicated when the bus master
drives SDA from high to low while the SCL signal is
high. All read and write transactions begin with a Start
condition. An operation in progress can be aborted by
asserting a Start condition at any time. Aborting an
operation using the Start condition will ready the
FM24C04B for a new operation.
If during operation the power supply drops below the
specified V
DD
minimum, the system should issue a
Start condition prior to performing another operation.
Data/Address Transfer
All data transfers (including addresses) take place
while the SCL signal is high. Except under the two
conditions described above, the SDA signal should not
change while SCL is high.
Acknowledge
The Acknowledge takes place after the 8
th
data bit has
been transferred in any transaction. During this state
the transmitter should release the SDA bus to allow the
receiver to drive it. The receiver drives the SDA signal
low to acknowledge receipt of the byte. If the receiver
does not drive SDA low, the condition is a No-
Acknowledge and the operation is aborted.
The receiver could fail to acknowledge for two distinct
reasons. First, if a byte transfer fails, the No-
Acknowledge ends the current operation so that the
device can be addressed again. This allows the last
Rev. 3.0
Jan. 2012
byte to be recovered in the event of a communication
error. Second and most common, the receiver does
not acknowledge the data to deliberately end an
operation. For example, during a read operation, the
FM24C04B will continue to place data onto the bus
as long as the receiver sends acknowledges (and
clocks). When a read operation is complete and no
more data is needed, the receiver must not
acknowledge the last byte. If the receiver
acknowledges the last byte, this will cause the
FM24C04B to attempt to drive the bus on the next
clock while the master is sending a new command
such as a Stop command.
Slave Address
The first byte that the FM24C04B expects after a
start condition is the slave address. As shown in
Figure 4, the slave address contains the device type,
the device select, the page of memory to be
accessed, and a bit that specifies if the transaction is
a read or a write.
Bits 7-4 are the device type and should be set to
1010b for the FM24C04B. The device type allows
other types of functions to reside on the 2-wire bus
within an identical address range. Bits 3-2 are the
device address. If bit 3 matches the A2 pin and bit 2
matches the A1 pin the device will be selected. Bit 1
is the page select. It specifies the 256-byte block of
memory that is targeted for the current operation. Bit
0 is the read/write bit. A 0 indicates a write
operation.
Word Address
After the FM24C04B (as receiver) acknowledges the
slave ID, the master will place the word address on
the bus for a write operation. The word address is
the lower 8-bits of the address to be combined with
the 1-bit page select to specify exactly the byte to be
written. The complete 9-bit address is latched
internally.
Page 4 of 12
FM24C04B
Memory Operation
The FM24C04B is designed to operate in a manner
very similar to other 2-wire interface memory
products. The major differences result from the
higher performance write capability of FRAM
technology. These improvements result in some
differences between the FM24C04B and a similar
configuration EEPROM during writes. The complete
operation for both writes and reads is explained
below.
Write Operation
All writes begin with a slave address then a word
address. The bus master indicates a write operation
by setting the LSB of the Slave address to a 0. After
addressing, the bus master sends each byte of data to
the memory and the memory generates an
acknowledge condition. Any number of sequential
bytes may be written. If the end of the address range
is reached internally, the address counter will wrap
from 1FFh to 000h.
Unlike other nonvolatile memory technologies, there
is no write delay with FRAM. The entire memory
cycle occurs in less time than a single bus clock.
Therefore any operation including read or write can
occur immediately following a write. Acknowledge
polling, a technique used with EEPROMs to
determine if a write is complete is unnecessary and
will always return a done condition.
An actual memory array write occurs after the 8
th
data bit is transferred. It will be complete before the
acknowledge is sent. Therefore if the user desires to
abort a write without altering the memory contents,
this should be done using a start or stop condition
prior to the 8
th
data bit. The FM24C04B needs no
page buffering.
The memory array can be write protected using the
WP pin. Pulling WP high will disable writes to the
entire array. The FM24C04B will not acknowledge
data bytes that are written when write protect is
asserted. In addition, the address counter will not
increment if writes are attempted. Pulling WP low
(V
SS
) will deactivate this feature.
Figures 5 and 6 below illustrate both a single-byte
and multiple- byte write cases.
Figure 4. Slave Address
No word address occurs for a read operation. Reads
always use the lower 8-bits that are held internally in
the address latch and the 9
th
address bit is part of the
slave address. Reads always begin at the address
following the previous access. A random read address
can be loaded by doing a write operation as explained
below.
After transmission of each data byte, just prior to the
acknowledge, the FM24C04B increments the internal
address latch. This allows the next sequential byte to
be accessed with no additional addressing. After the
last address (1FFh) is reached, the address latch will
roll over to 000h. There is no limit to the number of
bytes that can be accessed with a single read or write
operation.
Data Transfer
After all address information has been transmitted,
data transfer between the bus master and the
FM24C04B can begin. For a read operation the
FM24C04B will place 8 data bits on the bus then wait
for an acknowledge. If the acknowledge occurs, the
next sequential byte will be transferred. If the
acknowledge is not sent, the read operation is
concluded. For a write operation, the FM24C04B will
accept 8 data bits from the master then send an
acknowledge. All data transfer occurs MSB (most
significant bit) first.
Rev. 3.0
Jan. 2012
Page 5 of 12
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