High Performance Dual 14-Bit, 125MSPS ADC
ISLA224P12
The ISLA224P12 is a high performance dual 14-bit 125MSPS
analog-to-digital converter offering very high dynamic range and
low power consumption. It carries the export control
classification number 3A991.c.3 and can be exported without a
license to most countries, including China and Russia. It is part of
a pin-compatible family of 12- to 16-bit A/Ds with maximum
sample rates ranging from 125 to 500MSPS. This allows a design
using the ISLA224P12 to accommodate any of the other
pin-compatible A/Ds with minimal changes.
The ISLA224P12 is very flexible and can be designed into a wide
variety of systems. A serial peripheral interface (SPI) port allows
access to its extensive configurability as well as provides digital
control over various analog parameters such as input gain and
offset. Digital output data is presented in selectable LVDS or
CMOS formats in half-width, double data rate (DDR). Operating
from a 1.8V supply, performance is specified over the full
industrial temperature range (-40°C to +85°C).
Features
• License-free Import for most countries including China and
Russia (ECCN 3A991.c.3)
• Multi-ADC Support
- SPI Programmable Fine Gain and Offset Control
- Multiple ADC Synchronization
- Optimized Output Timing
• Clock Duty Cycle Stabilizer
• Nap and Sleep Modes
• Programmable Built-in Test Patterns
• DDR LVDS-Compatible or LVCMOS Outputs
• Data Output Clock
Key Specifications
• SNR @ 125MSPS
- 74.7dBFS f
IN
= 30MHz
- 70.2dBFS f
IN
= 363MHz
• SFDR @ 125MSPS
- 86dBc f
IN
= 30MHz
- 79dBc f
IN
= 363MHz
• Total Power Consumption = 590mW
Applications
• Radar Array Processing
• Software Defined Radio
• Broadband Communications
• High Performance Data Acquisition
• Communications Test Equipment
CLKDIVRSTP
CLKDIVRSTN
Pin-Compatible Family
OVDD
AVDD
CLKDIV
MODEL
ISLA224P25
CLKOUTP
CLKOUTN
RESOLUTION
14
14
14
12
12
12
SPEED
(MSPS)
250
200
130
250
200
130
CLKP
CLKN
CLOCK
MANAGEMENT
ISLA224P20
ISLA224P13
ISLA222P25
ISLA222P20
ISLA222P13
VINBP
VINBN
SHA
14-BIT
125 MSPS
ADC
VREF
DIGITAL
ERROR
CORRECTION
D[13:0]P
D[13:0]N
ORP
ORN
OUTFMT
OUTMODE
VCM
VINAN
VINAP
SHA
14-BIT
125 MSPS
ADC
VREF
+
1.25V
-
–
SPI
CONTROL
RESETN
CSB
SCLK
SDIO
SDO
NAPSLP
August 17, 2012
FN7983.3
1
OVSS
AVSS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Copyright Intersil Americas Inc. 2012. All Rights Reserved
Intersil (and design) and FemtoCharge are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISLA224P12
Pin Configuration- LVDS Mode
ISLA224P12
(72 LD QFN)
TOP VIEW
OVDD
OVSS
OVSS
AVDD
AVDD
AVDD
SCLK
SDIO
ORN
ORP
SDO
CSB
D0N
D1N
D2N
55
54 D3P
53 D3N
52 D4P
51 D4N
50 D5P
49 D5N
48 CLKOUTP
47 CLKOUTN
46 RLVDS
45 OVSS
44 D6P
43 D6N
42 D7P
41 D7N
40 D8P
39 D8N
Thermal Pad Not Drawn to Scale.
Consult Mechanical Drawing for
Physical Dimensions.
38 D9P
Connect Thermal Pad to AVSS
37 D9N
19
AVDD
20
AVDD
21
AVDD
22
CLKP
23
CLKN
24
CLKDIVRSTP
25
CLKDIVRSTN
26
OVSS
27
OVDD
28
D13N
29
D13P
30
D12N
31
D12P
32
OVDD
33
D11N
34
D11P
35
D10N
36
D10P
D0P
D1P
D2P
56
72
DNC
DNC
NAPSLP
VCM
AVSS
VINBP
VINBN
AVSS
AVDD
AVDD
AVSS
VINAN
VINAP
AVSS
CLKDIV
DNC
DNC
RESETN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
Pin Descriptions - 72 Ld QFN, LVDS Mode
PIN NUMBER
1, 2, 16, 17
9, 10, 19, 20, 21, 70, 71, 72
5, 8, 11, 14
27, 32, 62
26, 45, 61, 65
3
4
6, 7
LVDS PIN NAME
DNC
AVDD
AVSS
OVDD
OVSS
NAPSLP
VCM
VINBP, VINBN
Do Not Connect
1.8V Analog Supply
Analog Ground
1.8V Output Supply
Output Ground
Tri-Level Power Control (Nap, Sleep modes)
Common Mode Output
Channel B Analog Input Positive, Negative
LVDS PIN FUNCTION
2
FN7983.3
August 17, 2012
ISLA224P12
Pin Descriptions - 72 Ld QFN, LVDS Mode
PIN NUMBER
12, 13
15
18
22, 23
24, 25
28, 29
30, 31
33, 34
35, 36
37, 38
39, 40
41, 42
43, 44
46
47, 48
49, 50
51, 52
53, 54
55, 56
57, 58
59, 60
63, 64
66
67
68
69
Exposed Paddle
LVDS PIN NAME
VINAN, VINAP
CLKDIV
RESETN
CLKP, CLKN
CLKDIVRSTP, CLKDIVRSTN
D13N, D13P
D12N, D12P
D11N, D11P
D10N, D10P
D9N, D9P
D8N, D8P
D7N, D7P
D6N, D6P
RLVDS
CLKOUTN, CLKOUTP
D5N, D5P
D4N, D4P
D3N, D3P
D2N, D2P
D1N, D1P
D0N, D0P
ORN, ORP
SDO
CSB
SCLK
SDIO
AVSS
(Continued)
LVDS PIN FUNCTION
Channel A Analog Input Negative, Positive
Tri-Level Clock Divider Control
Power On Reset (Active Low)
Clock Input True, Complement
Synchronous Clock Divider Reset True, Complement
LVDS Bit 13 (MSB) Output Complement, True
LVDS Bit 12 Output Complement, True
LVDS Bit 11 Output Complement, True
LVDS Bit 10 Output Complement, True
LVDS Bit 9 Output Complement, True
LVDS Bit 8 Output Complement, True
LVDS Bit 7 Output Complement, True
LVDS Bit 6 Output Complement, True
LVDS Bias Resistor (connect to OVSS with 1%10kΩ)
LVDS Clock Output Complement, True
LVDS Bit 5 Output Complement, True
LVDS Bit 4 Output Complement, True
LVDS Bit 3 Output Complement, True
LVDS Bit 2 Output Complement, True
LVDS Bit 1 Output Complement, True
LVDS Bit 0 (LSB) Output Complement, True
LVDS Over Range Complement, True
SPI Serial Data Output
SPI Chip Select (active low)
SPI Clock
SPI Serial Data Input/Output
Analog Ground
3
FN7983.3
August 17, 2012
ISLA224P12
Pin Configuration- CMOS Mode
ISLA224P12
(72 LD QFN)
TOP VIEW
OVDD
OVSS
OVSS
AVDD
AVDD
AVDD
SCLK
SDIO
DNC
DNC
DNC
DNC
55
54 D3
53 DNC
52 D4
51 DNC
50 D5
49 DNC
48 CLKOUT
47 DNC
46 RLVDS
45 OVSS
44 D6
43 DNC
42 D7
41 DNC
40 D8
39 DNC
Thermal Pad Not Drawn to Scale.
Consult Mechanical Drawing for
Physical Dimensions.
38 D9
Connect Thermal Pad to AVSS
37 DNC
19
AVDD
20
AVDD
21
AVDD
22
CLKP
23
CLKN
24
CLKDIVRSTP
25
CLKDIVRSTN
26
OVSS
27
OVDD
28
DNC
29
D13
30
DNC
31
D12
32
OVDD
33
DNC
34
D11
35
DNC
36
D10
SDO
CSB
OR
D0
D1
72
DNC
DNC
NAPSLP
VCM
AVSS
VINBP
VINBN
AVSS
AVDD
AVDD
AVSS
VINAN
VINAP
AVSS
CLKDIV
DNC
DNC
RESETN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
Pin Descriptions - 72 Ld QFN, CMOS Mode
PIN NUMBER
1, 2, 16, 17, 28, 30, 33, 35, 37,
39, 41, 43, 47, 49, 51, 53, 55,
57, 59, 63
9, 10, 19, 20, 21, 70, 71, 72
5, 8, 11, 14
27, 32, 62
26, 45, 61, 65
3
4
CMOS PIN NAME
DNC
Do Not Connect
CMOS PIN FUNCTION
AVDD
AVSS
OVDD
OVSS
NAPSLP
VCM
1.8V Analog Supply
Analog Ground
1.8V Output Supply
Output Ground
Tri-Level Power Control (Nap, Sleep modes)
Common Mode Output
4
D2
FN7983.3
August 17, 2012
ISLA224P12
Pin Descriptions - 72 Ld QFN, CMOS Mode
PIN NUMBER
6, 7
12, 13
15
18
22, 23
24, 25
29
31
34
36
38
40
42
44
46
48
50
52
54
56
58
60
64
66
67
68
69
Exposed Paddle
CMOS PIN NAME
VINBP, VINBN
VINAN, VINAP
CLKDIV
RESETN
CLKP, CLKN
CLKDIVRSTP, CLKDIVRSTN
D13
D12
D11
D10
D9
D8
D7
D6
RLVDS
CLKOUT
D5
D4
D3
D2
D1
D0
OR
SDO
CSB
SCLK
SDIO
AVSS
(Continued)
CMOS PIN FUNCTION
Channel B Analog Input Positive, Negative
Channel A Analog Input Negative, Positive
Tri-Level Clock Divider Control
Power On Reset (Active Low)
Clock Input True, Complement
Synchronous Clock Divider Reset True, Complement
CMOS Bit 13 (MSB) Output
CMOS Bit 12 Output
CMOS Bit 11 Output
CMOS Bit 10 Output
CMOS Bit 9 Output
CMOS Bit 8 Output
CMOS Bit 7 Output
CMOS Bit 6 Output
LVDS Bias Resistor (connect to OVSS with 1%10kΩ)
CMOS Clock Output
CMOS Bit 5 Output
CMOS Bit 4 Output
CMOS Bit 3 Output
CMOS Bit 2 Output
CMOS Bit 1 Output
CMOS Bit 0 (LSB) Output
CMOS Over Range
SPI Serial Data Output
SPI Chip Select (active low)
SPI Clock
SPI Serial Data Input/Output
Analog Ground
Ordering Information
PART NUMBER
(Notes 1, 2)
ISLA224P12IRZ
ISLA224IR72EV1Z
KMB-001LEVALZ
KMB-001CEVALZ
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate-e4
termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. For Moisture Sensitivity Level (MSL), please see device information page for
ISLA224P12.
For more information on MSL please see techbrief
TB363.
PART
MARKING
ISLA224P12 IRZ
TEMP. RANGE
(°C)
-40°C to +85°C
PACKAGE
(Pb-free)
72 Ld QFN
PKG.
DWG. #
L72.10x10E
Evaluation Board - Supports 125/130/200/250 Speed Grades
LVDS Motherboard (Interfaces with ISLA224IR72EV1Z operating in LVDS Output Mode)
CMOS Motherboard (Interfaces with ISLA224IR72EV1Z operating in CMOS Output Mode)
5
FN7983.3
August 17, 2012
Microcontroller MCU
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