Product Data Sheet
FX-500
Low Jitter Frequency Translator
Features
•
Complete Frequency Translator to 77.760 MHz
•
3.3 Volt or 5.0 Volt Supply
•
Capable of locking to an 8 kHz pulse/BITS clock
•
Tri-State Output allows board test
•
J-lead Ceramic Package
•
Advanced Customer ASIC Technology
•
Absolute Pull Range Performance to ±100 ppm
•
CMOS Output
•
Commercial or Industrial Temperature Range
•
EIA Compatible Tape and Reel Packaging
•
RoHS/Lead Free Compliant
Description
The FX-500 is a complete crystal-based frequency
translator used in communications applications
where low jitter is paramount.
Performance advantages include superior jitter
performance, high output frequencies and small
package size. Advanced custom ASIC technology
results in a highly robust, reliable and predictable
device.
The device is packaged in a 6 pin J-Lead ceramic
package with a hermetic seam welded lid.
Applications
•
Frequency Translation, Clock Smoothing
•
Telecom – SONET/SDH/ATM
•
Datacom – DSLAM, DSLAR, Access Nodes
•
Cable Modem Head End
•
Base Station – GSM, CDMA
•
Military Communications
Figure 1. Functional Block Diagram
Tel: 1-88-VECTRON-1
•
Web:
www.vectron.com
Page 1 of 6
Rev: 20Jun06
Vectron International, 267 Lowell Road, Hudson, NH 03051
FX-500 Low Jitter Frequency Translator
Electrical Performance
Parameter
Supply Voltage
Supply Current @ 19.44 MHz
48.408 MHz
77.760 MHz
Input
Input Low Level Voltage
Input High Level Voltage
Frequency
Pulse Width
Output
Output High Level Voltage
Output Low Level Voltage
Transition Times
Rise Time
Fall Time
Duty Cycle
< 60 MHz
> 60 MHz
Nominal Output Frequency
Absolute Pull Range
Leakage Current of Input
Loop Bandwidth (-3 dB), 8 kHz Input
Jitter (Application: 8 kHz to 77.76 MHz)
rms
peak/peak
peak/peak
Operating Temperature
Package Size
Symbol
V
DD
V
DD
I
DD
I
DD
I
DD
V
IL
V
IH
f
IN
Minimum
3.0
4.5
Typical
3.3
5.0
15
25
35
Maximum
3.6
5.5
20
30
40
0.3* V
DD
Units
V
V
mA
mA
mA
V
V
Hz
Ns
V
V
ns
ns
%
Notes
1,5
0.7* V
DD
1k
6
0.9*V
DD
77.76 M
V
OH
V
OL
t
R
t
F
D
0.1*V
DD
1.8
1.8
45
40
0.100
See Part Numbering
-1
10
4.7
44
0.003
1
3.0
3.0
55
60
77.76
2
3,5
MHz
ppm
µA
Hz
ps
ps
UI
°C
Mm
4
f
O
APR
I
C
BW
Φ
J
T
OP
-40
+85
5
9.0 x 14.0 x 4.5
1. A 0.1
µF
low frequency tantalum bypass capacitor in parallel with a 0.01
µF
high frequency ceramic capacitor is recommended.
2. Figure 3 defines the waveform parameters. Figure 2 illustrates the standard test conditions under which these parameters are specified
and tested.
3. Duty cycle is defined as (on time÷period), with VS = VDD/2, per figure 3. Duty cycle is measured with a 15pf load per figure 2.
4. Other frequencies may be available, please contact factory.
5. See Standard Frequencies and Ordering Information (Pg 6).
I
DD
30k
2k
V
DD
+
-
.
1uF
.01uF
6
1
f
IN
5
2
4
3
15pF
Figure 2. Test Circuit
Figure 3. Output Waveform
Vectron International, 267 Lowell Road, Hudson, NH 03051
Page 2 of 6
Tel: 1-88-VECTRON-1
•
Web:
www.vectron.com
Rev: 20Jun06
FX-500 Low Jitter Frequency Translator
Outline Diagram
6
5
4
.026
[0.66]
Suggested Pad Layout
FX-500-LAC-GNK
8K000/77M760
VI 142
1
2
3
Figu
Figu
.300
[7.62]
.087
[2.21]
.100
[2.54]
.200
[5.08]
inch
[m m ]
Figure 4.
Figure 5.
Pin Out
Pin #
1
2
3
4
5
6
1.
2.
Symbol
f
IN
Tri-state
GND
f
O
2
LD
V
DD
1
Function
Input Frequency
Logic Low = Output Disable
Logic High = Output Enabled
Case and Electrical Ground
Output Frequency
Lock Detect
Power Supply Voltage (3.3 V
±
0.3 or 5.0 V
±
0.5)
Tristate is driven to logic high or logic low; there is no internal pull up or pull down resistor.
LD is an open collector output requiring a 30k ohm pullup resistor to V
DD
. LD output is logic high under locked condition, logic low for no
input at f
IN
, and for “out-of-lock” condition LD transitions between logic low and logic high at the phase detector
frequency.
Tape and Reel (EIA-481-2-A)
Po
ØDo
W2
F
W
D
C
N
A
P1
W1
B
Tape Dimensions (mm)
Dimension
Tolerance
FX-500
Reel Dimensions (mm)
Do
Typ
1.5
W
Typ
24
F
Typ
11.5
Po
Typ
4
P1
Typ
12
A
Typ
330
B
Min
1.78
C
Typ
13
D
Min
20.2
N
Min
100
W1
Typ
24.4
W2
Max
30.4
# Per
Reel
200
Vectron International, 267 Lowell Road, Hudson, NH 03051
Page 3 of 6
Tel: 1-88-VECTRON-1
•
Web:
www.vectron.com
Rev: 20Jun06
FX-500 Low Jitter Frequency Translator
Absolute Maximum Ratings
Parameter
Power Supply
Storage Temperature
Soldering Temp/Time
Symbol
V
CC
TS
T
LS
Ratings
0 to 7
-55 to 125
260/40
Unit
Vdc
°C
°C/sec
Stresses in excess of the absolute maximum ratings can permanently damage the device. Functional operation is
not implied at these or any other conditions in excess of conditions represented in the operational sections of this
data sheet. Exposure to absolute maximum ratings for extended periods may adversely affect device reliability.
Reliability
The FX-500 family is capable of meeting the following qualification tests:
Environmental Compliance
Parameter
Mechanical Shock
Mechanical Vibration
Solderability
Gross and Fine Leak
Resistance to Solvents
Conditions
MIL-STD-883, Method 2002
MIL-STD-883, Method 2007
MIL-STD-883, Method 2003
MIL-STD-883, Method 1014
MIL-STD-883, Method 2016
Handling Precautions
Although ESD protection circuitry has been designed into the FX-500 proper precautions should be taken when
handling and mounting. VI employs a human body model and a charged-device model (CDM) for ESD
susceptibility testing and design protection evaluation.
ESD Ratings
Model
Human Body Model
Charged Device Model
Minimum
1000 V
1000 V
Conditions
MIL-STD 883, Method 3015
JEDEC, JESD22-C101
Vectron International, 267 Lowell Road, Hudson, NH 03051
Page 4 of 6
Tel: 1-88-VECTRON-1
•
Web:
www.vectron.com
Rev: 20Jun06
FX-500 Low Jitter Frequency Translator
Reflow Profile (IPC/JEDEC J-STD-020C)
Parameter
Symbol
PreHeat Time
Ramp Up
Time Above 217
o
C
Time To Peak Temperature
Time At 260
o
C
Ramp Down
t
S
R
UP
t
L
t
AMB-P
t
P
R
DN
260
Value
60 sec Min, 180 sec Max
3
o
C/sec Max
60 sec Min, 150 sec Max
480 sec Max
20 sec Min, 40 sec Max
6
o
C/sec Max
Temperature (DegC)
The FX-500 has been qualified to meet the JEDEC
standard for Pb-Free assembly. The temperatures
and time intervals listed are based on the Pb-Free
small body requirements. The temperatures refer to
the topside of the package, measured on the
package body surface. The FX-500 device is
hermetically sealed so an aqueous wash is not an
issue.
.
t
L
R
UP
t
P
R
DN
217
200
150
t
S
t
AMB-P
25
Time (sec)
Vectron International, 267 Lowell Road, Hudson, NH 03051
Page 5 of 6
Tel: 1-88-VECTRON-1
•
Web:
www.vectron.com
Rev: 20Jun06
FPGA/CPLD
京公网安备 11010802033920号
EEWORLD
