EEWORLDEEWORLDEEWORLD

Part Number

Search

DNR-09PCJB-SG15

Description
D Type Connector, 9 Contact(s), Male, 0.109 inch Pitch, Solder Terminal, #4-40, Receptacle
CategoryThe connector    The connector   
File Size224KB,3 Pages
ManufacturerKeltron Connector Company
Download Datasheet Parametric View All

DNR-09PCJB-SG15 Overview

D Type Connector, 9 Contact(s), Male, 0.109 inch Pitch, Solder Terminal, #4-40, Receptacle

DNR-09PCJB-SG15 Parametric

Parameter NameAttribute value
Reach Compliance Codeunknown
ECCN codeEAR99
Other featuresFOOTPRINT,.318\"
body width0.492 inch
subject depth0.488 inch
body length1.213 inch
Body/casing typeRECEPTACLE
Contact to complete cooperationAU ON NI
Contact completed and terminatedGOLD
Contact point genderMALE
Contact materialCOPPER ALLOY
contact modeSTAGGERED
Contact styleRND PIN-SKT
Dielectric withstand voltage1000VAC V
Insulation resistance1000000000 Ω
Insulator colorBLACK
insulator materialGLASS FILLED POLYESTER
Manufacturer's serial numberDNR
Plug contact pitch0.109 inch
Match contact row spacing0.112 inch
Installation option 1#4-40
Installation option 2CLINCH NUT JACKSCREW
Installation methodRIGHT ANGLE
Installation typeBOARD
PCB row number2
Number of rows loaded2
Maximum operating temperature105 °C
Minimum operating temperature-55 °C
PCB contact patternSTAGGERED
PCB contact row spacing2.8448 mm
Plating thickness15u inch
Rated current (signal)5 A
reliabilityCOMMERCIAL
Shell surfaceTIN
Shell materialSTEEL
Terminal pitch2.7686 mm
Termination typeSOLDER
Total number of contacts9
2010 Guangxi College Student Electronic Design Competition List
[i=s] This post was last edited by paulhyde on 2014-9-15 09:48 [/i] 1. Basic instrument list 20MHz ordinary oscilloscope (dual channel, external trigger input, with X-axis input, optional with Z-axis ...
huangxiao0801 Electronics Design Contest
Does the connection between Cyclone IV FPGA and CAN controller SJA1000 require a level conversion chip?
FPGA's IO is powered by 3.3V, SJA1000 is powered by 5V...
shen19891209 FPGA/CPLD
Xu Jinglei's blog ranks first in the world
Character InformationName: Xu Jinglei Gender: FemaleDate of Birth: 1974.04.16 English name:Zodiac sign: Aries Blood type: OHobbies: music, leisure, sports Height: 168 cmCountry of Citizenship: Birthpl...
gaoyanmei Talking
How to design a delay device using VHDL
The input is some randomly generated signals, and all these input signals are required to be output sequentially after a delay of 100 clock cycles. How should this be designed ? The order of the input...
eeleader-mcu FPGA/CPLD
Notes on posting in this forum
[i=s]This post was last edited by paulhyde on 2014-9-15 09:52[/i] When discussing graduation project issues in this forum, please state the content of the design and the general software concept. If y...
zhangf1982 Electronics Design Contest
FPGA application three levels
FPGA applications can be divided into three levels: circuit design, product design, and system design. 1. System-level application   System-level applications combine FPGA with traditional computer te...
suifeng654456 FPGA/CPLD

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 204  1837  2030  682  1299  5  37  41  14  27 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号