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5962R9574701VRC

Description
HCT SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDIP20, METAL SEALED, SIDE BRAZED, CERAMIC, DIP-20
Categorylogic    logic   
File Size277KB,11 Pages
ManufacturerIntersil ( Renesas )
Websitehttp://www.intersil.com/cda/home/
Download Datasheet Parametric Compare View All

5962R9574701VRC Overview

HCT SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDIP20, METAL SEALED, SIDE BRAZED, CERAMIC, DIP-20

5962R9574701VRC Parametric

Parameter NameAttribute value
Parts packaging codeDIP
package instructionDIP, DIP20,.3
Contacts20
Reach Compliance Codeunknown
seriesHCT
JESD-30 codeR-CDIP-T20
JESD-609 codee4
Load capacitance (CL)50 pF
Logic integrated circuit typeBUS DRIVER
MaximumI(ol)0.006 A
Number of digits8
Number of functions1
Number of ports2
Number of terminals20
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Output characteristics3-STATE
Output polarityTRUE
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDIP
Encapsulate equivalent codeDIP20,.3
Package shapeRECTANGULAR
Package formIN-LINE
power supply5 V
Prop。Delay @ Nom-Sup30 ns
propagation delay (tpd)34 ns
Certification statusNot Qualified
Filter level38535V;38534K;883S
Maximum seat height5.08 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal surfaceGOLD
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
total dose100k Rad(Si) V
width7.62 mm
HCTS373MS
August 1995
Radiation Hardened
Octal Transparent Latch, Three-State
Pinouts
20 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T20
TOP VIEW
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
1
2
3
4
5
6
7
8
9
20 VCC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 LE
Features
• 3 Micron Radiation Hardened CMOS SOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm
2
/mg
• Single Event Upset (SEU) Immunity < 2 x 10
-9
Errors/Bit-
Day (Typ)
• Dose Rate Survivability: >1 x 10
• Dose Rate Upset >10
10
RAD
12
RAD (Si)/s
(Si)/s 20ns Pulse
• Latch-Up Free Under Any Conditions
• Fanout (Over Temperature Range)
- Bus Driver Outputs - 15 LSTTL Loads
• Military Temperature Range: -55
o
C to +125
o
C
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Compatibility
- VIL = 0.8V Max
- VIH = VCC/2 Min
• Input Current Levels Ii
5µA at VOL, VOH
GND 10
Description
The Intersil HCTS373MS is a Radiation Hardened octal transpar-
ent three-state latch with an active-low output enable. The out-
puts are transparent to the inputs when the Latch Enable (LE) is
HIGH. When the Latch Enable (LE) goes LOW, the data is
latched. The Output Enable (OE) controls the three-state outputs.
When the Output Enable (OE) is HIGH, the outputs are in the
high impedance state. The latch operation is independent of the
state of the Output Enable.
The HCTS373MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCTS373MS is supplied in a 20 lead Ceramic flatpack (K
suffix) or a SBDIP Package (D suffix).
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND
20 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F20
TOP VIEW
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
LE
Ordering Information
PART NUMBER
HCTS373DMSR
HCTS373KMSR
HCTS373D/Sample
HCTS373K/Sample
HCTS373HMSR
TEMPERATURE RANGE
-55
o
C to +125
o
C
-55
o
C to +125
o
C
+25
o
C
+25
o
C
+25
o
C
SCREENING LEVEL
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
PACKAGE
20 Lead SBDIP
20 Lead Ceramic Flatpack
20 Lead SBDIP
20 Lead Ceramic Flatpack
DB NA
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
©
Intersil Corporation 1999
Spec Number
File Number
638
518636
2131.2

5962R9574701VRC Related Products

5962R9574701VRC
Description HCT SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDIP20, METAL SEALED, SIDE BRAZED, CERAMIC, DIP-20
Parts packaging code DIP
package instruction DIP, DIP20,.3
Contacts 20
Reach Compliance Code unknown
series HCT
JESD-30 code R-CDIP-T20
JESD-609 code e4
Load capacitance (CL) 50 pF
Logic integrated circuit type BUS DRIVER
MaximumI(ol) 0.006 A
Number of digits 8
Number of functions 1
Number of ports 2
Number of terminals 20
Maximum operating temperature 125 °C
Minimum operating temperature -55 °C
Output characteristics 3-STATE
Output polarity TRUE
Package body material CERAMIC, METAL-SEALED COFIRED
encapsulated code DIP
Encapsulate equivalent code DIP20,.3
Package shape RECTANGULAR
Package form IN-LINE
power supply 5 V
Prop。Delay @ Nom-Sup 30 ns
propagation delay (tpd) 34 ns
Certification status Not Qualified
Filter level 38535V;38534K;883S
Maximum seat height 5.08 mm
Maximum supply voltage (Vsup) 5.5 V
Minimum supply voltage (Vsup) 4.5 V
Nominal supply voltage (Vsup) 5 V
surface mount NO
technology CMOS
Temperature level MILITARY
Terminal surface GOLD
Terminal form THROUGH-HOLE
Terminal pitch 2.54 mm
Terminal location DUAL
total dose 100k Rad(Si) V
width 7.62 mm

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