EEWORLDEEWORLDEEWORLD

Part Number

Search

A3P400-2FG484IY

Description
Field Programmable Gate Array
CategoryProgrammable logic devices    Programmable logic   
File Size6MB,221 Pages
ManufacturerMicrochip
Websitehttps://www.microchip.com
Download Datasheet Parametric View All

A3P400-2FG484IY Overview

Field Programmable Gate Array

A3P400-2FG484IY Parametric

Parameter NameAttribute value
Reach Compliance Codecompliant
Revision 18
DS0097
ProASIC3 Flash Family FPGAs
with Optional Soft ARM Support
Features and Benefits
High Capacity
• 15 K to 1 M System Gates
• Up to 144 Kbits of True Dual-Port SRAM
• Up to 300 User I/Os
Advanced I/O
• 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Wide Range Power Supply Voltage Support per JESD8-B,
Allowing I/Os to Operate from 2.7 V to 3.6 V
• Bank-Selectable I/O Voltages—up to 4 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X
and LVCMOS
2.5 V / 5.0 V Input
• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and
M-LVDS (A3P250 and above)
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold Sparing I/Os
• Programmable Output Slew Rate
and Drive Strength
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the ProASIC3 Family
• Six CCC Blocks, One with an Integrated PLL
• Configurable Phase-Shift, Multiply/Divide, Delay Capabilities
and External Feedback
• Wide Input Frequency Range (1.5 MHz to 350 MHz)
• 1 Kbit of FlashROM User Nonvolatile Memory
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)
• True Dual-Port SRAM (except ×18)
Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
Process
• Instant On Level 0 Support
• Single-Chip Solution
• Retains Programmed Design when Powered Off
High Performance
• 350 MHz System Performance
• 3.3 V, 66 MHz 64-Bit PCI
In-System Programming (ISP) and Security
• ISP Using On-Chip 128-Bit Advanced Encryption Standard
(AES) Decryption (except ARM
®
-enabled ProASIC
®
3 devices)
via JTAG (IEEE 1532–compliant)
• FlashLock
®
to Secure FPGA Contents
Clock Conditioning Circuit (CCC) and PLL
Low Power
• Core Voltage for Low Power
• Support for 1.5 V-Only Systems
• Low-Impedance Flash Switches
Embedded Memory
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
ARM Processor Support in ProASIC3 FPGAs
ProASIC3 Devices
A3P015
1
A3P030
A3P060 A3P125
A3P250
A3P400
A3P600
2
Cortex-M1 Devices
M1A3P250 M1A3P400
M1A3P600
System Gates
15,000
30,000
60,000 125,000
250,000
400,000
600,000
Typical Equivalent Macrocells
128
256
512
1,024
2,048
VersaTiles (D-flip-flops)
384
768
1,536
3,072
6,144
9,216
13,824
RAM Kbits (1,024 bits)
18
36
36
54
108
4,608-Bit Blocks
4
8
8
12
24
FlashROM Kbits
1
1
1
1
1
1
1
3
Secure (AES) ISP
Yes
Yes
Yes
Yes
Yes
Integrated PLL in CCCs
1
1
1
1
1
4
VersaNet Globals
6
6
18
18
18
18
18
I/O Banks
2
2
2
2
4
4
4
Maximum User I/Os
49
81
96
133
157
194
235
Notes:
1. A3P015 is not recommended for new designs.
2. Refer to the
Cortex-M1
product brief for more information.
3. AES is not available for Cortex-M1 ProASIC3 devices.
4. Six chip (main) and three quadrant global networks are available for A3P060 and above.
5. The M1A3P250 device does not support this package.
6. For higher densities and support of additional features, refer to the
ProASIC3E Flash Family FPGAs
datasheet.
7. Package not available.
• M1 ProASIC3 Devices—ARM
®
Cortex
®
-M1 Soft Processor
Available with or without Debug
A3P1000
M1A3P1000
1,000,000
24,576
144
32
1
Yes
1
18
4
300
† A3P015 and A3P030 devices do not support this feature.
‡ Supported only by A3P015 and A3P030 devices.
March 2016
© 2016 Microsemi Corporation
I
STM32 serial port problem
Previously, the serial port of STM32F103VCT6 was used to send and receive data normally under IAR4.42. Later, it was ported to KEIL and used STM32F100VBT6. Other functions were normal, but the serial ...
suyanqin stm32/stm8
MMC program verification can
[i=s] This post was last edited by paulhyde on 2014-9-15 08:56 [/i] I use c51 and it works...
csj19861219 Electronics Design Contest
Smartphone era: dreams come true
[i=s]This post was last edited by jameswangsynnex on 2015-3-3 19:56[/i]On September 25, Apple's iPhone 4 began to sell well in mainland China. "One day, all consumer electronics will essentially becom...
探路者 Mobile and portable
TI launches highly flexible power line communication solution - EEWORLD first
A friend sent it to me. She took the trouble to find someone to translate it and shared it with everyone.Introduction Power line communication uses the existing power line infrastructure as a low-cost...
soso Industrial Control Electronics
Little Watermelon Learns Renesas MCU (0) First Sight
Thanks to eeworld for hosting so many great events. This time I had the opportunity to get in touch with Renesas' MCU. Let me be honest here. Actually, I am not too interested in this MCU. The purpose...
574433742 Renesas Electronics MCUs
Today at 10:00 AM, live broadcast with awards: [High-performance i.MX RT processors help smart nodes achieve machine learning without Internet access...
[align=left][size=14px][backcolor=red][font=微软雅黑][size=4][color=#ffffff]Live Topic: [/color][/size][/font][/backcolor][/size][/align][align=left][size=14px][b]High-performance i.MX RT processors help ...
EEWORLD社区 MCU

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 160  1588  204  2201  1394  4  32  5  45  29 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号