PIC24F16KL402 FAMILY
Low-Power, Low-Cost, General Purpose
16-Bit Flash Microcontrollers with XLP Technology
Power Management Modes:
•
•
•
•
•
Run – CPU, Flash, SRAM and Peripherals On
Doze – CPU Clock Runs Slower than Peripherals
Idle – CPU Off, SRAM and Peripherals On
Sleep – CPU, Flash and Peripherals Off and SRAM On
Low-Power Consumption:
- Run mode currents of 150 µA/MHz typical at 1.8V
- Idle mode currents under 80 µA/MHz at 1.8V
- Sleep mode currents as low as 30 nA at +25°C
- Watchdog Timer as low as 210 nA at +25°C
Peripheral Features:
• High-Current Sink/Source (18 mA/18 mA) on All
I/O Pins
• Configurable Open-Drain Outputs on Digital I/O Pins
• Up to Three External Interrupt Sources
• Two 16-Bit Timer/Counters with Selectable Clock
Sources
• Up to Two 8-Bit Timers/Counters with Programmable
Prescalers
• Two Capture/Compare/PWM (CCP) modules:
- Modules automatically configure and drive I/O
- 16-bit Capture with max. resolution 40 ns
- 16-bit Compare with max. resolution 83.3 ns
- 1-bit to 10-bit PWM resolution
• Up to One Enhanced CCP module:
- Backward compatible with CCP
- 1, 2 or 4 PWM outputs
- Programmable dead time
- Auto-shutdown on external event
• Up to Two Master Synchronous Serial Port modules
(MSSPs) with Two Modes of Operation:
- 3-wire SPI (all four modes)
- I
2
C™ Master, Multi-Master and Slave modes and
7-Bit/10-Bit Addressing
• Up to Two UART modules:
- Supports RS-485, RS-232 and LIN/J2602
- On-chip hardware encoder/decoder for IrDA
®
- Auto-wake-up on Start bit
- Auto-Baud Detect (ABD)
- Two-byte transmit and receive FIFO buffers
Peripherals
10-Bit A/D (ch)
UART w/IrDA
®
2
2
2
2
2
2
1
1
1
1
Comparators
CCP/ECCP
8/16-Bit
Timers
High-Performance CPU:
• Modified Harvard Architecture
• Up to 16 MIPS Operation @ 32 MHz
• 8 MHz Internal Oscillator:
- 4x PLL option
- Multiple divide options
• 17-Bit x 17-Bit Single-Cycle Hardware
Fractional/integer Multiplier
• 32-Bit by 16-Bit Hardware Divider
• 16 x 16-Bit Working Register Array
• C Compiler Optimized Instruction Set
Architecture (ISA):
- 76 base instructions
- Flexible addressing modes
• Linear Program Memory Addressing
• Linear Data Memory Addressing
• Two Address Generation Units (AGU) for Separate
Read and Write Addressing of Data Memory
Device
Pins
Flash
Program
(bytes)
16K
8K
16K
8K
8K
8K
8K
8K
4K
4K
Data
(bytes)
Data
EEPROM
(bytes)
512
512
512
512
256
256
—
—
—
—
PIC24F16KL402
PIC24F08KL402
PIC24F16KL401
PIC24F08KL401
PIC24F08KL302
PIC24F08KL301
PIC24F08KL201
PIC24F08KL200
PIC24F04KL101
PIC24F04KL100
28
28
20
20
28
20
20
14
20
14
1024
1024
1024
1024
1024
1024
512
512
512
512
12
12
12
12
—
—
12
7
—
—
2
2
2
2
2
2
1
1
1
1
2/2
2/2
2/2
2/2
2/2
2/2
1/2
1/2
1/2
1/2
2/1
2/1
2/1
2/1
2/1
2/1
2/0
2/0
2/0
2/0
2
2
2
2
2
2
1
1
1
1
2011-2013 Microchip Technology Inc.
DS30001037C-page 1
Ultra Low-Power
Wake-up
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Memory
MSSP
PIC24F16KL402 FAMILY
Analog Features:
• 10-Bit, up to 12-Channel Analog-to-Digital (A/D)
Converter:
- 500 ksps conversion rate
- Conversion available during Sleep and Idle
• Dual Rail-to-Rail Analog Comparators with
Programmable Input/Output Configuration
• On-Chip Voltage Reference
• Fail-Safe Clock Monitor (FSCM) Operation:
- Detects clock failure and switches to on-chip,
Low-Power RC (LPRC) oscillator
• Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)
• Flexible Watchdog Timer (WDT):
- Uses its own Low-Power RC oscillator
- Windowed operating modes
- Programmable period of 2 ms to 131s
• In-Circuit Serial Programming™ (ICSP™) and
In-Circuit Emulation (ICE) via 2 Pins
• Programmable High/Low-Voltage Detect (HLVD)
• Programmable Brown-out Reset (BOR):
- Configurable for software controlled operation and
shutdown in Sleep mode
- Selectable trip points (1.8V, 2.7V and 3.0V)
- Low-power 2.0V POR re-arm
Special Microcontroller Features:
• Operating Voltage Range of 1.8V to 3.6V
• 10,000 Erase/Write Cycle Endurance Flash Program
Memory, Typical
• 100,000 Erase/Write Cycle Endurance Data
EEPROM, Typical
• Flash and Data EEPROM Data Retention:
40 Years Minimum
• Self-Programmable under Software Control
• Programmable Reference Clock Output
DS30001037C-page 2
2011-2013 Microchip Technology Inc.
PIC24F16KL402 FAMILY
Pin Diagrams: PIC24FXXKL302/402
28-Pin SPDIP/SSOP/SOIC
(1)
MCLR/V
PP
/RA5
V
REF
+/CV
REF
+/AN0/SDA2/CN2/RA0
CV
REF
-/V
REF
-/AN1/CN3/RA1
PGED1/AN2/ULPWU/C1IND/C2INB/U2TX/CN4/RB0
PGEC1/AN3/C1INC/C2INA/U2RX/CN5/RB1
AN4/C1INB/C2IND/T3G/U1RX/CN6/RB2
C1INA/C2INC/SCL2/CN7/RB3
V
SS
OSCI/AN13/CLKI/CN30/RA2
OSCO/AN14/CLKO/CN29/RA3
SOSCI/AN15/U2RTS/CN1/RB4
SOSCO/SCLKI/U2CTS/CN0/RA4
V
DD
PGED3/ASDA1
(2)
/SCK2/CN27/RB5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
DD
V
SS
AN9/T3CK/REFO/SS1/CN11/RB15
CV
REF
/AN10/C1OUT/FLT0/INT1/CN12/RB14
AN11/SDO1/CN13/RB13
AN12/HLVDIN/SS2/CCP2/CN14/RB12
PGEC2/SCK1/P1C/CN15/RB11
PGED2/SDI1/P1B/CN16/RB10
C2OUT/CCP1/P1A/INT2/CN8/RA6
SDI2/CCP3/CN9/RA7
SDA1/T1CK/U1RTS/P1D/CN21/RB9
SCL1/U1CTS/CN22/RB8
U1TX/INT0/CN23/RB7
PGEC3/ASCL1
(2)
/SDO2/CN24/RB6
PGED1/AN2/ULPWU/C1IND/C2INB/U2TX/CN4/RB0
PGEC1/AN3/C1INC/C2INA/U2RX/CN5/RB1
AN4/C1INB/C2IND/T3G/U1RX/CN6/RB2
C1INA/C2INC/SCL2/CN7/RB3
V
SS
OSCI/AN13/CLKI/CN30/RA2
OSCO/AN14/CLKO/CN29/RA3
CV
REF
-/V
REF
-/AN1/CN3/RA1
V
REF
+/CV
REF
+/AN0/SDA2/CN2/RA0
MCLR/ V
PP
/RA5
V
DD
V
SS
AN9/T3CK/REFO/SS1/CN11/RB15
CV
REF
/AN10/C1OUT/FLT0/INT1/CN12/RB14
28 27 26 25 24 23 22
1
2
3
PIC24FXXKL302
(2)
4
PIC24FXXKL402
5
6
7
8 9 10 11 12 13 14
SOSCI/AN15/U2RTS/CN1/RB4
SOSCO/SCLKI/U2CTS/CN0/RA4
V
DD
(2)
/SCK2/CN27/RB5
PGED3/ASDA1
PGEC3/ASCL1
(2)
/SDO2/CN24/RB6
U1TX/INT0/CN23/RB7
SCL1/U1CTS/CN22/RB8
21
20
19
18
17
16
15
AN11/SDO1/CN13/RB13
AN12/HLVDIN/SS2/CCP2/CN14/RB12
PGEC2/SCK1/P1C/CN15/RB11
PGED2/SDI1/P1B/CN16/RB10
C2OUT/CCP1/P1A/INT2/CN8/RA6
SDI2/CCP3/CN9/RA7
SDA1/T1CK/U1RTS/P1D/CN21/RB9
28-Pin QFN
(1)
Contact your Microchip sales team for Chip Scale Package (CSP) availability.
Note 1:
2:
Analog features (indicated in
red)
are not available on PIC24FXXKL302 devices.
Alternate location for I
2
C™ functionality of MSSP1, as determined by the I2C1SEL Configuration bit.
2011-2013 Microchip Technology Inc.
PIC24FXXKL302
(2)
PIC24FXXKL402
DS30001037C-page 3
PIC24F16KL402 FAMILY
Pin Diagrams: PIC24FXXKL301/401
20-Pin PDIP/SSOP/SOIC
(1)
MCLR/V
PP
/RA5
PGEC2/V
REF
+/CV
REF
+/AN0/SDA2/SDI2/CN2/RA0
PGED2/CV
REF
-/V
REF
-/AN1/SDO2/CN3/RA1
PGED1/AN2/ULPWU/C1IND/C2INB/U2TX/P1C/CN4/RB0
PGEC1/AN3/C1INC/C2INA/U2RX/CN5/RB1
PGEC3/SOSCO/SCLKI/U2CTS/CN0/RA4
OSCI/AN13/C1INB/C2IND/CLKI/CN30/RA2
OSCO/AN14/C1INA/C2INC/CLKO/CN29/RA3
PGED3/SOSCI/AN15/U2RTS/CN1/RB4
AN4/T3G/U1RX/CN6/RB2
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
DD
V
SS
AN9/SCL2/T3CK/REFO/SCK2/CN11/RB15
CV
REF
/AN10/SDI1/C1OUT/FLT0/INT1/CN12/RB14
AN11/SDO1/P1D/CN13/RB13
AN12/HLVDIN/SCK1/SS2/CCP2/CN14/RB12
C2OUT/CCP1/P1A/INT2/CN8/RA6
SDA1/T1CK/U1RTS/CCP3/CN21/RB9
SCL1/U1CTS/SS1/CN22/RB8
U1TX/INT0/CN23/RB7
20-Pin QFN
(1)
PGED2/CV
REF
-/V
REF
-/AN1/SDO2/CN3/RA1
PGEC2/V
REF
+/CV
REF
+/AN0/SDA2/SDI2/CN2/RA0
MCLR/V
PP
/RA5
V
DD
V
SS
20 19 18 17 16
PIC24FXXKL301
(2)
PIC24FXXKL401
PGED1/AN2/ULPWU/C1IND/C2INB/U2TX/P1C/CN4/RB0
PGEC1/AN3/C1INC/C2INA/U2RX/CN5/RB1
AN4/T3G/U1RX/CN6/RB2
OSCI/AN13/C1INB/C2IND/CLKI/CN30/RA2
OSCO/AN14/C1INA/C2INC/CLKO/CN29/RA3
15
1
(2)
14
2
PIC24FXXKL301
3
PIC24FXXKL401
13
12
4
11
5
6 7 8 9 10
PGED3/SOSCI/AN15/U2RTS/CN1/RB4
PGEC3/SOSCO/SCLKI/U2CTS/CN0/RA4
U1TX/INT0/CN23/RB7
SCL1/U1CTS/SS1/CN22/RB8
SDA1/T1CK/U1RTS/CCP3/CN21/RB9
AN9/SCL2/T3CK/REFO/SCK2/CN11/RB15
CV
REF
/AN10/SDI1/C1OUT/FLT0/INT1/CN12/RB14
AN11/SDO1/P1D/CN13/RB13
AN12/HLVDIN/SCK1/SS2/CCP2/CN14/RB12
C2OUT/CCP1/P1A/INT2/CN8/RA6
Note 1:
2:
Analog features (indicated in
red)
are not available on PIC24FXXKL301 devices.
Alternate location for I
2
C™ functionality of MSSP1, as determined by the I2C1SEL Configuration bit.
DS30001037C-page 4
2011-2013 Microchip Technology Inc.
PIC24F16KL402 FAMILY
Pin Diagrams: PIC24FXXKL10X/20X
PGED2/CV
REF
-/V
REF
-/AN1/CN3/RA1
PGEC2/V
REF
+/CV
REF
+/AN0/CN2/RA0
MCLR/VPP/RA5
VDD
VSS
20 19 18 17 16
PGED1/AN2/ULPWU/C1IND/CN4/RB0
PGEC1/AN3/C1INC/CN5/RB1
AN4/T3G/U1RX/CN6/RB2
OSCI/AN13/C1INB/CLKI/CN30/RA2
OSCO/AN14/C1INA/CLKO/CN29/RA3
15
1
14
2
PIC24FXXKL101
(2)
13
3
PIC24FXXKL201
12
4
11
5
6 7 8 9 10
PGED3/SOSCI/AN15/CN1/RB4
PGEC3/SOSCO/SCLKI/CN0/RA4
U1TX/INT0/CN23/RB7
SCL1/U1CTS/SS1/CN22/RB8
SDA1/T1CK/U1RTS/CN21/RB9
AN9/T3CK/REFO/CN11/RB15
CV
REF
/AN10/SDI1/C1OUT/INT1/CN12/RB14
AN11/SDO1/CN13/RB13
AN12/HLVDIN/SCK1/CCP2/CN14/RB12
CCP1/INT2/CN8/RA6
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
DD
V
SS
AN9/T3CK/REFO/CN11/RB15
CV
REF
/AN10/SDI1/C1OUT/INT1/CN12/RB14
AN11/SDO1/CN13/RB13
AN12/HLVDIN/SCK1/CCP2/CN14/RB12
CCP1/INT2/CN8/RA6
SDA1/T1CK/U1RTS/CN21/RB9
SCL1/U1CTS/SS1/CN22/RB8
U1TX/INT0/CN23/RB7
PIC24FXXKL100
(2)
PIC24FXXKL200
1
2
3
4
5
6
7
20-Pin QFN
(1)
20-Pin PDIP/SSOP/SOIC
(1)
MCLR/V
PP
/RA5
PGEC2/V
REF
+/CV
REF
+/AN0/CN2/RA0
PGED2/CV
REF
-/V
REF
-/AN1/CN3/RA1
PGED1/AN2/ULPWU/C1IND/CN4/RB0
PGEC1/AN3/C1INC/CN5/RB1
AN4/T3G/U1RX/CN6/RB2
OSCI/AN13/C1INB/CLKI/CN30/RA2
OSCO/AN14/C1INA/CLKO/CN29/RA3
PGED3/SOSCI/AN15/CN1/RB4
PGEC3/SOSCO/SCLKI/CN0/RA4
14-Pin PDIP/TSSOP
(1)
MCLR/V
PP
/RA5
PGEC2/V
REF
+/CV
REF
+/AN0/CN2/RA0
PGED2/CV
REF
-/V
REF
-/AN1/ULPWU/CN3/RA1
OSCI/AN13/C1INB/CLKI/CN30/RA2
OSCO/AN14/C1INA/CLKO/CN29/RA3
PGED3/SOSCI/AN15/HLVDIN/CN1/RB4
PGEC3/SOSCO/SCLKI/CN0/RA4
14
13
12
11
10
9
8
V
DD
V
SS
AN9/T3CK/REFO/U1RX/SS1/INT0/CN11/RB15
CV
REF
/AN10/T3G/U1TX/SDI1/C1OUT/INT1/CN12/RB14
CCP1/INT2/CN8/RA6
SDA1/T1CK/U1RTS/SDO1/CCP2/CN21/RB9
SCL1/U1CTS/SCK1/CN22/RB8
Note 1:
2:
Analog features (indicated in
red)
are not available on PIC24FXXKL100/101 devices.
Alternate location for I
2
C™ functionality of MSSP1, as determined by the I2C1SEL Configuration bit.
2011-2013 Microchip Technology Inc.
PIC24FXXKL101
(2)
PIC24FXXKL201
DS30001037C-page 5
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