EEWORLDEEWORLDEEWORLD

Part Number

Search

HPD041UMDVO00X

Description
Board Connector, 41 Contact(s), 2 Row(s), Male, Straight, 0.1 inch Pitch, Solder Terminal, Receptacle,
CategoryThe connector    The connector   
File Size485KB,30 Pages
ManufacturerSmiths Group
Download Datasheet Parametric View All

HPD041UMDVO00X Overview

Board Connector, 41 Contact(s), 2 Row(s), Male, Straight, 0.1 inch Pitch, Solder Terminal, Receptacle,

HPD041UMDVO00X Parametric

Parameter NameAttribute value
Reach Compliance Codeunknown
ECCN codeEAR99
body width0.252 inch
subject depth0.315 inch
body length2.717 inch
Body/casing typeRECEPTACLE
Connector typeBOARD CONNECTOR
Contact to complete cooperationAU
Contact completed and terminatedTIN
Contact point genderMALE
Contact materialCOPPER ALLOY
contact modeSTAGGERED
Contact resistance7 mΩ
Contact styleRND PIN-SKT
Dielectric withstand voltage1400VAC V
Durability2000 Cycles
Insulation resistance5000000000 Ω
JESD-609 codee3
Plug contact pitch0.1 inch
Match contact row spacing0.1 inch
Installation methodSTRAIGHT
Installation typeBOARD
Number of connectorsONE
PCB row number2
Number of rows loaded2
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
PCB contact patternSTAGGERED
PCB contact row spacing2.54 mm
Plating thickness50u inch
Rated current (signal)4 A
reliabilityCOMMERCIAL
Terminal pitch2.54 mm
Termination typeSOLDER
Total number of contacts41
ASTASTHPD
Series
2 & 3 Contact Row
Signal Connectors
Product description
Standard-density signal PCB connector
(2,54 mm x 2,54 mm pitch)
Approvals
BS 9525 N0001, Mil-C-55302 & ESA SCC 3401
Features
Large number of pin count options
Large number of termination options
Large number of guide options
High reliability contacts
Advantages
Versatile range covering Cardfile, Stacking and
Flying-lead applications
Markets
Mil/Aero Space, Marine, Rail & Industrial
Technical Characteristics
Contact Number
Contact Diameter
Current Rating
Contact Resistance
Contact mating force
Contact Life Cycle
Breakdown Voltage Between Contacts
Dielectric Withstanding Voltage
Temperature Rating
Insulation Resistance
Insulator Material
Contact
- Material
- Plating (Mating surfaces)
Guide Hardware
- Material
- Plating
Plating Reference
17, 29, 33, 41, 48, 53, 62, 65, 72, 80, 84, 96, 98, 119, 120, 149 & 160
0,60 mm
4A
7 Milli-Ohm (max)
0,28 N (average)
> 2000
1920 V AC (min) [sea level]
1400 V AC (min) [sea level]
-55 to +125 Degree C
5 Gigo-Ohm @ 500 V DC (min)
DAP
Copper alloy
1,27 micro-metres Gold Plate (min)
Stainless steel BS 303
Passivated
N/A
The following unshrouded sizes are qualified to:
MIL-C-55302/159 and 162
17, 29, 41, 53 and 65 position
MIL-C-55302/160 and 163
72, 84, 96 and 120 position
MIL-C-55302/161 and 164
160 position
BS 9525 N0001/1982
17, 29, 33, 41, 53, 65, 72, 84, 96 and 120 position
BS 9525 F0041/1989
17, 29, 33, 41, 53, 65, 72, 84, and 96 position
Incorporates BS 9525 N0001 testing but includes Gunfire vibration test.
BS 9525 F0053/1995
Additional specification to BS 9525 N0001 with extra terminations.
BS 9525-F-0016/1995
48, 62, 80, 98, 119, 149 and 160 (Solid insulator) position
The following shrouded sizes are qualified to:
BS 9525-F-0016/1995
48, 98, 119 and 160 position
Space qualification:
APRIL
ESA/SCC 5401/016/017
37
2005
Problems encountered in Xilinx simulation
Started : "Creating Tbw file". ERROR:ProjectMgmt - TOE: ITclInterp::ExecuteCmd gave Tcl result 'invalid command name "0"'. Tcl_ErrnoId: unknown error Tcl_ErrnoMsg: No error _cmd: ::xilinx::Dpm::dpm_ch...
eeleader FPGA/CPLD
[Uncle T's Library] "Analysis and Design of Analog Integrated Circuits (Fourth Edition)"
[p=24, null, left][color=rgb(86, 86, 86)][backcolor=rgb(237, 235, 235)][font=微软雅黑][size=14px][url=https://download.eeworld.com.cn/detail/tyw/301799?src=2114][color=#0066cc]Chinese version: "Analysis a...
tyw Download Centre
Motion Estimation Algorithm Design and FPGA Implementation.pdf
Motion Estimation Algorithm Design and FPGA Implementation.pdf...
zxopenljx FPGA/CPLD
Question: The problem of unstable sampling on the rising edge of the clock
A very simple code written in Verilog, roughly: reg[1:0] q; //q is the data generated by calling the IP core fifo, the default is reg type output assign data_out={{4{q[0]}},{4{q[1]}}}; //data_out is t...
xyw FPGA/CPLD
Why does the network port chip (971) have the function of encoding and decoding?
So the data sent out through the network port chip is not the original data given by the CPU?...
mbwr Embedded System
After the TPS54540DDA chip is loaded, the voltage drops and becomes unstable.
Urgent! Urgent! Urgent! Please help! See the attached schematic diagram. The specific situation is as follows: input 24V, expected output +5V, but the actual output is only +3.8V, and it is very unsta...
WangTao Analogue and Mixed Signal

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2160  1813  567  2080  2242  44  37  12  42  46 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号