Crystal or Differential to Differential
Clock Fanout Buffer
General Description
The IDT8T39S10I is a high-performance clock fanout buffer. The
input clock can be selected from two differential inputs or one crystal
input. The internal oscillator circuit is automatically disabled if the
crystal input is not selected. The crystal pin can be driven by
single-ended clock when crystal is bypassed.The selected signal is
distributed to ten differential outputs which can be configured as
LVPECL, LVDS or HSCL outputs. In addition, an LVCMOS output is
provided. All outputs can be disabled into a high-impedance state.
The device is designed for signal fanout of high-frequency, low
phase-noise clock and data signal. The outputs are at a defined level
when inputs are open circuit or tied to ground. It is designed to
operate from a 3.3V or 2.5V core power supply, and either a 3.3V or
2.5V output operating supply.
IDT8T39S10I
DATASHEET
Features
•
•
•
•
•
Two differential reference clock input pairs
Differential input pairs can accept the following differential input
levels: LVPECL, LVDS, HCSL
Crystal Oscillator Interface
Crystal input frequency range: 10MHz to 40MHz
Maximum Output Frequency
LVPECL - 2GHz
LVDS
- 2GHz
HCSL
- 250MHz
LVCMOS - 250MHz
Two banks, each has five differential output pairs that can be
configured as LVPECL or LVDS or HCSL
One single-ended reference output with synchronous enable to
avoid clock glitch
Output skew: (Bank A and Bank B at the same output level)
70ps (max)
Part-to-part skew: 250ps (max)
Additive RMS phase jitter: 0.153ps (typical)
Supply voltage modes:
V
DD
/V
DDO
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging
•
•
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IDT8T39S10NLGI REVISION A MARCH 18. 2014
1
©2014 Integrated Device Technology, Inc.
IDT8T39S10I Data Sheet
CRYSTAL OR DIFFERENTIAL-TO-DIFFERENTIAL CLOCK FANOUT BUFFER
Block Diagram
SMODEA[1:0]
Pulldown
REF_SEL[1:0]
Pulldown
CLK0
nCLK0
CLK1
nCLK1
XTAL_IN
XTAL_OUT
Pulldown
Pullup/Pulldown
00
QA0
nQA0
QA1
nQA1
QA2
nQA2
QA3
nQA3
QA4
nQA4
QB0
nQB0
QB1
nQB1
QB2
nQB2
QB3
nQB3
QB4
nQB4
Pulldown
Pullup/Pulldown
01
OSC
10
or
11
IREF
SMODEB[1:0]
OE_SE
Pulldown
REFOUT
Pulldown
SYNC
Pin Assignment
nQB0
nQB1
nQB2
nQB3
36
35
34
33
32
31
30
29
28
27
26
GND
37
IREF
38
nQB4
25
24
23
22
V
DDO
V
DDO
QB0
QB1
QB2
QB3
QB4
GND
SMODEB0
REF_SEL1
nCLK0
CLK0
REF_SEL0
GND
XTAL_OUT
XTAL_IN
V
DD
SMODEA0
GND
SMODEB1
39
nCLK1
40
CLK1
41
V
DD
GND
REFOUT
42
43
44
V
DDO
45
OE_SE
46
SMODEA1
47
GND
48
IDT8T39S10I
48-Lead VFQFN
7.0mm x 7.0mm x 0.925mm, package body
5.65mm x 5.65mm Epad size
NL Package
Top View
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
nQA0
nQA1
nQA2
nQA3
IDT8T39S10NLGI REVISION A MARCH 18. 2014
2
nQA4
V
DDO
V
DDO
QA0
QA1
QA2
QA3
QA4
©2013 Integrated Device Technology, Inc.
IDT8T39S10I Data Sheet
CRYSTAL OR DIFFERENTIAL-TO-DIFFERENTIAL CLOCK FANOUT BUFFER
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
1, 2
3, 4
5, 8, 29, 32, 45
6, 7
9, 10
11, 12
13, 18, 24,
37, 43, 48
14, 47
15, 42
16,
17
19,
22
20
21
23, 39
25, 26
27, 28
30, 31
33, 34
35, 36
38
40
41
44
46
Name
QA0, nQA0
QA1, nQA1
V
DDO
QA2, nQA2
QA3, nQA3
QA4, nQA4
GND
SMODEA0,
SMODEA1
V
DD
XTAL_IN,
XTAL_OUT
REF_SEL0,
REF_SEL1
CLK0
nCLK0
SMODEB0,
SMODEB1
nQB4, QB4
nQB3, QB3
nQB2, QB2
nQB1, QB1
nQB0, QB0
IREF
nCLK1
CLK1
REFOUT
OE_SE
Output
Output
Power
Output
Output
Output
Power
Input
Power
Input
Input
Input
Input
Input
Output
Output
Output
Output
Output
Input
Input
Input
Output
Input
Pulldown
Pullup/
Pulldown
Pulldown
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Pulldown
Type
Description
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.
Output supply pins.
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.
Power supply ground.
Output driver select for Bank A outputs. See Table 3D for function.
LVCMOS/LVTTL interface levels.
Power supply pins.
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
Input clock selection. LVCMOS/LVTTL interface levels.
See Table 3A for function.
Non-inverting differential clock.
Inverting differential clock. Internal resistor bias to V
DD
/2.
Output driver select for Bank B outputs. See Table 3D for function.
LVCMOS/LVTTL interface levels.
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.
An external fixed precision resistor (475) from this pin to ground provides a
reference current used for HCSL mode. QXx, nQXx clock outputs.
Inverting differential clock. Internal resistor bias to V
DD
/2.
Non-inverting differential clock.
Single-ended reference clock output. LVCMOS/LVTTL interface levels
Output enable. LVCMOS/LVTTL interface levels. See Table 3B.
NOTE:
Pulldown
and
Pullup
refer to an internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
IDT8T39S10NLGI REVISION A MARCH 18. 2014
3
©2013 Integrated Device Technology, Inc.
IDT8T39S10I Data Sheet
CRYSTAL OR DIFFERENTIAL-TO-DIFFERENTIAL CLOCK FANOUT BUFFER
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
R
PULLUP
C
PD
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Power
Dissipation
Capacitance
Qx, nQx
V
DDO
= 3.3V
V
DDO
= 3.3V
V
DDO
= 2.5V
V
DDO
= 3.3V
V
DDO
= 2.5V
Test Conditions
SMODEx[0:1],
REF_SEL[0:1], OE_SE pins
Minimum
Typical
4
51
51
3.5
8
7
15
20
Maximum
Units
pF
k
k
pF
pF
pF
C
PD
R
OUT
Power Dissipation Capacitance
REFOUT
Output
Impedance
REFOUT
REFOUT
Function Tables
Table 3A. REF_SELx Function Table
Control Input
REF_SEL[1:0]
00 (default)
01
10
11
CLK0, nCLK0
CLK1, nCLK1
XTAL
XTAL
Selected Input Reference Clock
Table 3B. OE_SE Function Table
OE_SE
0 (default)
1
REFOUT
High-Impedance
Enabled
NOTE: Synchronous output enable to avoid clock glitch.
Table 3C. Input/Output Operation Table, OE_SE
Input Status
OE_SE
0 (default)
1
REF_SEL [1:0]
Don’t care
10 or 11
CLKx and nCLKx
Don’t Care
Don’t Care
CLK0 and nCLK0 are both open circuit
1
00 (default)
CLK0 and nCLK0 are tied to ground
CLK0 is high, nCLK0 is low
CLK0 is low, nCLK0 is high
CLK1 and nCLK1 are both open circuit
1
01
CLK1 and nCLK1 are tied to ground
CLK1 is high, nCLK1 is low
CLK1 is low, nCLK1 is high
Output State
REFOUT
High Impedance
Fanout crystal oscillator
Logic low
Logic low
Logic High
Logic Low
Logic low
Logic low
Logic High
Logic Low
IDT8T39S10NLGI REVISION A MARCH 18. 2014
4
©2013 Integrated Device Technology, Inc.
IDT8T39S10I Data Sheet
CRYSTAL OR DIFFERENTIAL-TO-DIFFERENTIAL CLOCK FANOUT BUFFER
Table 3D. Input/Output Operation Table, SMODEA
Input Status
SMODEA[1:0]
11
00, 01 or 10
REF_SEL[1:0]
Don’t care
10 or 11
CLKx and nCLKx
Don’t Care
Don’t Care
CLK0 and nCLK0 are both open circuit
CLK0 and nCLK0 are tied to ground
00, 01 or 10
00 (default)
CLK0 is high, nCLK0 is low
CLK0 is low, nCLK0 is high
CLK1 and nCLK1 are both open circuit
CLK1 and CLK1 are tied to ground.
00, 01 or 10
01
CLK1 is high, nCLK1 is low
CLK1 is low, nCLK1 is high
Output State
QA[4:0], nQA[4:0]
High Impedance
Fanout crystal oscillator
QA[4:0] = Low
nQA4:0] = High
QA[4:0] = Low
nQA[4:0] = High
QA[4:0] = High
nQA[4:0] = Low
QA[4:0] = Low
nQA[4:0] = High
QA[4:0] = Low
nQA4:0] = High
QA[4:0] = Low
nQA[4:0] = High
QA[4:0] = High
nQA[4:0] = Low
QA[4:0] = Low
nQA4:0]=High
Table 3E. Input/Output Operation Table, SMODEB
Input Status
SMODEB[1:0]
11
00, 01 or 10
REF_SEL[1:0]
Don’t care
10 or 11
CLKx and nCLKx
Don’t Care
Don’t Care
CLK0 and nCLK0 are both open circuit
CLK0 and nCLK0 are tied to ground
00, 01 or 10
00 (default)
CLK0 is high, nCLK0 is low
CLK0 is low, nCLK0 is high
CLK1 and nCLK1 are both open circuit
CLK1 and nCLK1 are tied to ground
00, 01 or 10
01
CLK1 is high, nCLK1 is low
CLK1 is low, nCLK1 is high
Output State
QB[4:0], nQB[4:0]
High Impedance
Fanout crystal oscillator
QB[4:0] = Low
nQB4:0] = High
QB[4:0] = Low
nQB[4:0] = High
QB[4:0] = High
nQB[4:0] = Low
QB[4:0] = Low
nQB[4:0] = High
QB[4:0] = Low
nQB[4:0] = High
QB[4:0] = Low
nQB[4:0] = High
QB[4:0] = High
nQB[4:0] = Low
QB[4:0] = Low
nQB[4:0] = High
IDT8T39S10NLGI REVISION A MARCH 18. 2014
5
©2013 Integrated Device Technology, Inc.
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