IS61NVP12832EC-250B2LI datasheet, PDF

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IS61NVP12832EC-250B2LI: DescriptionZBT SRAM, 128KX32, 2.6ns, CMOS, PBGA119, BGA-119; Categorystorage storage; File Size3MB，40 Pages; ManufacturerISSI(Integrated Silicon Solution Inc.); Websitehttp://www.issi.com/; Environmental Compliance

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IS61NVP12832EC-250B2LI Overview

ZBT SRAM, 128KX32, 2.6ns, CMOS, PBGA119, BGA-119

IS61NVP12832EC-250B2LI Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Parts packaging code	BGA
package instruction	BGA, BGA119,7X17,50
Contacts	119
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	2.6 ns
Maximum clock frequency (fCLK)	250 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B119
JESD-609 code	e1
length	22 mm
memory density	4194304 bit
Memory IC Type	ZBT SRAM
memory width	32
Humidity sensitivity level	3
Number of functions	1
Number of terminals	119
word count	131072 words
character code	128000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	128KX32
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA119,7X17,50
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
power supply	2.5 V
Certification status	Not Qualified
Maximum seat height	3.5 mm
Maximum standby current	0.085 A
Minimum standby current	2.37 V
Maximum slew rate	0.26 mA
Maximum supply voltage (Vsup)	2.625 V
Minimum supply voltage (Vsup)	2.375 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	10
width	14 mm

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IS61(4)NLP12836EC/IS61(4)NVP12836EC/IS61(4)NLP12832EC

IS61(4)NVP12832EC/IS61(4)NLP25618EC/IS61(4)NVP25618EC

128K x36/32 and 256K x18 4Mb, ECC, PIPELINE 'NO WAIT' STATE

BUS SYNCHRONOUS SRAM

MAY 2013

FEATURES

•

100 percent bus utilization

•

No wait cycles between Read and Write

•

Internal self-timed write cycle

•

Individual Byte Write Control

•

Single R/W (Read/Write) control pin

•

Clock controlled, registered address, data and

control

•

Interleaved or linear burst sequence control

using MODE input

•

Three chip enables for simple depth

expansion and address pipelining

•

Power Down mode

•

Common data inputs and data outputs

•

/CKE pin to enable clock and suspend

operation

•

JEDEC 100-pin TQFP, 165-ball PBGA and

119-ball PBGA packages

•

Power supply:

NLP: V

3.3V (± 5%), V

DDQ

3.3V/2.5V (± 5%)

NVP: V

2.5V (± 5%), V

DDQ

2.5V (± 5%)

•

JTAG Boundary Scan for PBGA packages

•

Industrial and Automotive temperature support

•

Lead-free available

•

Error Detection and Error Correction

DESCRIPTION

The 4Mb product family features high-speed, low-

power synchronous static RAMs designed to

provide a burstable, high-performance, 'no wait'

state, device for networking and communications

applications. They are organized as 128K words

by 36 bits and 256K words by 18 bits, fabricated

with

ISSI's

advanced CMOS technology.

Incorporating a 'no wait' state feature, wait cycles

are eliminated when the bus switches from read

to write, or write to read. This device integrates a

2-bit burst counter, high-speed SRAM core, and

high-drive capability outputs into a single

monolithic circuit.

All synchronous inputs pass through registers are

controlled by a positive-edge-triggered single

clock input. Operations may be suspended and all

synchronous inputs ignored when Clock Enable,

/CKE is HIGH. In this state the internal device will

hold their previous values.

All Read, Write and Deselect cycles are initiated

by the ADV input. When the ADV is HIGH the

internal burst counter is incremented. New

external addresses can be loaded when ADV is

LOW.

Write cycles are internally self-timed and are

initiated by the rising edge of the clock inputs and

when /WE is LOW. Separate byte enables allow

individual bytes to be written.

A burst mode pin (MODE) defines the order of the

burst sequence. When tied HIGH, the interleaved

burst sequence is selected. When tied LOW, the

linear burst sequence is selected

250

2.6

250

200

3.1

200

Units

MHz

FAST ACCESS TIME

Symbol

MAX

Parameter

Clock Access Time

Cycle time

Frequency

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can

reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such

applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc.- www.issi.com

Rev. B

05/03/2013

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