Freescale Semiconductor
Data Sheet: Technical Data
Document Number: IMX6SDLCEC
Rev. 3, 03/2014
i.MX 6Solo/6DualLite
Applications Processors
for Consumer Products
MCIMX6SxExxxxxB
MCIMX6SxExxxxxC
MCIMX6UxExxxxxB
MCIMX6UxExxxxxC
MCIMX6SxDxxxxxB
MCIMX6SxDxxxxxC
MCIMX6UxDxxxxxB
MCIMX6UxDxxxxxC
Package Information
Plastic Package
BGA Case 2240 21 x 21 mm, 0.8 mm pitch
Ordering Information
See
Table 1 on page 3
1
Introduction
1
The i.MX 6Solo/6DualLite processors represent
Freescale Semiconductor’s latest achievement in
integrated multimedia-focused products offering high
performance processing with lower cost, as well as
optimization for low power consumption.
The processors feature Freescale’s advanced
implementation of single/dual ARM
®
Cortex
®
-A9 core,
which operates at speeds of up to 1 GHz. They include
2D and 3D graphics processors, 1080p video processing,
and integrated power management. Each processor
provides a 32/64-bit DDR3/LVDDR3/LPDDR2-800
memory interface and a number of other interfaces for
connecting peripherals, such as WLAN, Bluetooth
®
,
GPS, hard drive, displays, and camera sensors.
The i.MX 6Solo/6DualLite processors are specifically
useful for applications such as:
• Web and multimedia tablets
2
3
4
5
6
7
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . .3
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.3 Updated Signal Naming Convention . . . . . . . . . . . .8
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.1 Special Signal Considerations . . . . . . . . . . . . . . . .20
3.2 Recommended Connections for Unused Analog
Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .22
4.1 Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . .22
4.2 Power Supplies Requirements and Restrictions. . .32
4.3 Integrated LDO Voltage Regulator Parameters . . .34
4.4 PLL’s Electrical Characteristics. . . . . . . . . . . . . . . .36
4.5 On-Chip Oscillators . . . . . . . . . . . . . . . . . . . . . . . .37
4.6 I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . .38
4.7 I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . .43
4.8 Output Buffer Impedance Parameters . . . . . . . . . .47
4.9 System Modules Timing . . . . . . . . . . . . . . . . . . . . .50
4.10 General-Purpose Media Interface (GPMI) Timing .67
4.11 External Peripheral Interface Parameters. . . . . . . .75
Boot Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . .137
5.1 Boot Mode Configuration Pins . . . . . . . . . . . . . . .137
5.2 Boot Device Interface Allocation. . . . . . . . . . . . . .139
Package Information and Contact Assignments . . . . . .140
6.1 Updated Signal Naming Convention . . . . . . . . . .140
6.2 21x21 mm Package Information . . . . . . . . . . . . . .140
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
© 2012-2014 Freescale Semiconductor, Inc. All rights reserved.
Introduction
•
•
•
•
•
•
•
Web and multimedia tablets
Color eReaders
IPTV
Human Machine Interfaces (HMI)
Portable medical
IP phones
Home energy management systems
The i.MX 6Solo/6DualLite processors have some very exciting features, for example:
• Applications processors—The processors enhance the capabilities of high-tier portable
applications by fulfilling the ever increasing MIPS needs of operating systems and games.
Freescale’s Dynamic Voltage and Frequency Scaling (DVFS) provides significant power
reduction, allowing the device to run at lower voltage and frequency with sufficient MIPS for tasks,
such as audio decode.
• Multilevel memory system—The multilevel memory system of each processor is based on the L1
instruction and data caches, L2 cache, and internal and external memory. The processors support
many types of external memory devices, including DDR3, low voltage DDR3, LPDDR2, NOR
Flash, PSRAM, cellular RAM, NAND Flash (MLC and SLC), OneNAND™, and managed
NAND, including eMMC up to rev 4.4/4.41.
• Smart speed technology—The processors have power management throughout the IC that enables
the rich suite of multimedia features and peripherals to consume minimum power in both active
and various low power modes. Smart speed technology enables the designer to deliver a
feature-rich product, requiring levels of power far lower than industry expectations.
• Dynamic voltage and frequency scaling—The processors improve the power efficiency of devices
by scaling the voltage and frequency to optimize performance.
• Multimedia powerhouse—The multimedia performance of each processor is enhanced by a
multilevel cache system, NEON™ MPE (Media Processor Engine) co-processor, a multi-standard
hardware video codec, an image processing unit (IPU), a programmable smart DMA (SDMA)
controller, and an asynchronous sample rate converter.
• Powerful graphics acceleration—Each processor provides two independent, integrated graphics
processing units: an OpenGL
®
ES 2.0 3D graphics accelerator with a shader and a 2D graphics
accelerator.
• Interface flexibility—Each processor supports connections to a variety of interfaces: LCD
controller for up to two displays (including parallel display, HDMI1.4, MIPI display, and LVDS
display), dual CMOS sensor interface (parallel or through MIPI), high-speed USB on-the-go with
PHY, high-speed USB host with PHY, multiple expansion card ports (high-speed MMC/SDIO host
and other), 10/100/1000 Mbps Gigabit Ethernet controller two CAN ports, ESAI audio interface,
and a variety of other popular interfaces (such as UART, I
2
C, and I
2
S serial audio, and PCIe-II).
• Eink Panel Display Controller—The processors integrate EPD controller that supports E-INK
color and monochrome with up to 1650x2332 resolution and 5-bit grayscale (32-levels per color
channel).
i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 3
2
Freescale Semiconductor
Introduction
•
•
Advanced security—The processors deliver hardware-enabled security features that enable secure
e-commerce, digital rights management (DRM), information encryption, secure boot, and secure
software downloads. The security features are discussed in detail in the
i.MX 6Solo/6DualLite
Security Reference Manual
(IMX6DQ6SDLSRM).
Integrated power management—The processors integrate linear regulators and internally generate
voltage levels for different domains. This significantly simplifies system power management
structure.
1.1
Ordering Information
Table 1
provides examples of orderable part numbers covered by this data sheet.
Table 1
does not include
all possible orderable part numbers. The latest part numbers are available on the web page
freescale.com/imx6series. If the desired part number is not listed in
Table 1,
or there may be any questions
about available parts, see the web page freescale.com/imx6series or contact a Freescale representative.
Table 1. Example Orderable Part Numbers
Part Number
i.MX6 CPU
Solo/
DualLite
Options
Speed
Grade
1 GHz
1 GHz
1 GHz
1 GHz
1 GHz
1 GHz
1 GHz
1 GHz
1 GHz
1 GHz
1 GHz
1 GHz
Temperature
Grade
Package
MCIMX6U8DVM10AB DualLite With VPU, GPU, EPDC, MLB
2x ARM Cortex-A9 64-bit DDR
MCIMX6U8DVM10AC DualLite With VPU, GPU, EPDC, MLB
2x ARM Cortex-A9 64-bit DDR
MCIMX6U5DVM10AB DualLite With VPU, GPU, MLB, no EPDC
2x ARM Cortex-A9 64-bit DDR
MCIMX6U5DVM10AC DualLite With VPU, GPU, MLB, no EPDC
2x ARM Cortex-A9 64-bit DDR
MCIMX6U5EVM10AB DualLite With VPU, GPU, MLB, no EPDC
2x ARM Cortex-A9 64-bit DDR
MCIMX6U5EVM10AC DualLite With VPU, GPU, MLB, no EPDC
2x ARM Cortex-A9 64-bit DDR
MCIMX6S8DVM10AB
MCIMX6S8DVM10AC
MCIMX6S5DVM10AB
MCIMX6S5DVM10AC
MCIMX6S5EVM10AB
MCIMX6S5EVM10AC
Solo
Solo
Solo
Solo
Solo
Solo
With VPU, GPU, MLB, EPDC
1x ARM Cortex-A9 32-bit DDR
With VPU, GPU, MLB, EPDC
1x ARM Cortex-A9 32-bit DDR
With VPU, GPU, MLB, no EPDC
1x ARM Cortex-A9 32-bit DDR
With VPU, GPU, MLB, no EPDC
1x ARM Cortex-A9 32-bit DDR
With VPU, GPU, MLB, no EPDC
1x ARM Cortex-A9 32-bit DDR
With VPU, GPU, MLB, no EPDC
1x ARM Cortex-A9 32-bit DDR
Commercial 21 mm x 21 mm,
0.8 mm pitch, MAPBGA
Commercial 21 mm x 21 mm,
0.8 mm pitch, MAPBGA
Commercial 21 mm x 21 mm,
0.8 mm pitch, MAPBGA
Commercial 21 mm x 21 mm,
0.8 mm pitch, MAPBGA
Extended 21 mm x 21 mm,
Commercial 0.8 mm pitch, MAPBGA
Extended 21 mm x 21 mm,
Commercial 0.8 mm pitch, MAPBGA
Commercial 21 mm x 21 mm,
0.8 mm pitch, MAPBGA
Commercial 21 mm x 21 mm,
0.8 mm pitch, MAPBGA
Commercial 21 mm x 21 mm,
0.8 mm pitch, MAPBGA
Commercial 21 mm x 21 mm,
0.8 mm pitch, MAPBGA
Extended 21 mm x 21 mm,
Commercial 0.8 mm pitch, MAPBGA
Extended 21 mm x 21 mm,
Commercial 0.8 mm pitch, MAPBGA
i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 3
Freescale Semiconductor
3
Introduction
Figure 1
describes the part number nomenclature so that the users can identify the characteristics of the
specific part number they have (for example, cores, frequency, temperature grade, fuse options, and silicon
revision). The primary characteristic which describes which data sheet applies to a specific part is the
temperature grade (junction) field.
• The i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors data sheet
(IMX6SDLAEC) covers parts listed with an “A (Automotive temp)”
• The i.MX 6Solo/6DualLite Applications Processors for Consumer Products data sheet
(IMX6SDLCEC) covers parts listed with a “D (Commercial temp)” or “E (Extended Commercial
temp)”
• The i.MX 6Solo/6DualLite Applications Processors for Industrial Products data sheet
(IMX6SDLIEC) covers parts listed with “C (Industrial temp)”
Ensure to have the proper data sheet for specific part by verifying the temperature grade (junction) field
and matching it to the proper data sheet. If there will be any questions, visit see the web page
freescale.com/imx6series or contact a Freescale representative for details.
MC
IMX6
X
@
+
VV
$$
%
A
Qualification level
Prototype Samples
Mass Production
Special
MC
PC
MC
SC
Silicon revision
1
Rev 1.1
Rev 1.2
A
B
C
Fusing
Default settings
%
A
C
Part # series
i.MX 6DualLite
2x ARM Cortex-A9, 64-bit DDR
i.MX 6Solo
1x ARM Cortex-A9, 32-bit DDR
X
U
HDCP enabled
Frequency
S
800 MHz
2
1 GHz
3
$$
08
10
RoHS
Part differentiator
Consumer
Industrial
Automotive
Consumer
Automotive
Automotive
VPU
VPU
VPU
VPU
–
–
GPU
GPU
GPU
GPU
GPU
–
EPDC
–
–
–
–
–
MLB
–
MLB
MLB
MLB
MLB
@
8
7
6
5
4
1
Package type
MAPBGA 21 x 21 0.8mm
VM
Temperature Tj
Commercial: 0 to + 95
C
Extended commercial: -20 to + 105 C
Industrial: -40 to +105
C
Automotive: -40 to +
125
C
+
D
E
C
A
1. See the freescale.com\imx6series Web page for latest information on the available silicon revision.
2. If a 24 MHz input clock is used (required for USB), the maximum SoC speed is limited to 792 MHz.
3. If a 24 MHz input clock is used (required for USB), the maximum SoC speed is limited to 996 MHz.
Figure 1. Part Number Nomenclature—i.MX 6Solo and 6DualLite
1.2
Features
The i.MX 6Solo/6DualLite processors are based on ARM Cortex-A9 MPCore™ Platform, which has the
following features:
• The i.MX 6Solo supports single ARM Cortex-A9 MPCore (with TrustZone)
• The i.MX 6DualLite supports dual ARM Cortex-A9 MPCore (with TrustZone)
i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 3
4
Freescale Semiconductor
Introduction
•
The core configuration is symmetric, where each core includes:
— 32 KByte L1 Instruction Cache
— 32 KByte L1 Data Cache
— Private Timer and Watchdog
— Cortex-A9 NEON MPE (Media Processing Engine) Co-processor
The ARM Cortex-A9 MPCore™ complex includes:
• General Interrupt Controller (GIC) with 128 interrupt support
• Global Timer
• Snoop Control Unit (SCU)
• 512 KB unified I/D L2 cache:
— Used by one core in i.MX 6Solo
— Shared by two cores in i.MX 6DualLite
• Two Master AXI bus interfaces output of L2 cache
• Frequency of the core (including NEON and L1 cache), as per
Table 9.
• NEON MPE coprocessor
— SIMD Media Processing Architecture
— NEON register file with 32x64-bit general-purpose registers
— NEON Integer execute pipeline (ALU, Shift, MAC)
— NEON dual, single-precision floating point execute pipeline (FADD, FMUL)
— NEON load/store and permute pipeline
The SoC-level memory system consists of the following additional components:
— Boot ROM, including HAB (96 KB)
— Internal multimedia / shared, fast access RAM (OCRAM, 128 KB)
— Secure/non-secure RAM (16 KB)
• External memory interfaces: The i.MX 6Solo/6DualLite processors support latest, high volume,
cost effective handheld DRAM, NOR, and NAND Flash memory standards.
— 16/32-bit LP-DDR2-800, 16/32-bit DDR3-800 and LV-DDR3-800 in i.MX 6Solo; 16/32/64-bit
LP-DDR2-800, 16/32/64-bit DDR3-800 and LV-DDR3-800, supporting DDR interleaving
mode for 2x32 LPDDR2-800 in i.MX 6DualLite
— 8-bit NAND-Flash, including support for Raw MLC/SLC, 2 KB, 4 KB, and 8 KB page size,
BA-NAND, PBA-NAND, LBA-NAND, OneNAND™ and others. BCH ECC up to 40 bit.
— 16/32-bit NOR Flash. All WEIMv2 pins are muxed on other interfaces.
— 16/32-bit PSRAM, Cellular RAM
Each i.MX 6Solo/6DualLite processor enables the following interfaces to external devices (some of them
are muxed and not available simultaneously):
• Displays—Total five interfaces available. Total raw pixel rate of all interfaces is up to 450
Mpixels/sec, 24 bpp. Up to two interfaces may be active in parallel (excluding EPDC).
i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 3
Freescale Semiconductor
5
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