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BCM5700

Description
PCI - X 10/100/1000 BASE -T CONTROLLER
File Size151KB,2 Pages
ManufacturerETC
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BCM5700 Overview

PCI - X 10/100/1000 BASE -T CONTROLLER

BCM5700
PRODUCT
®
Brief
O F
B E N E F I T S
BCM5700 PCI-X 10/100/1000BASE-T CONTROLLER
B C M 5 7 0 0
F E AT U R E S
S U M M A R Y
10/100/1000 Mbps tri-speed media access controller (MAC)
with wire speed performance at all rates
Support for PCI v2.2, 32/64-bit, 33/66 MHz, and PCI-X v1.0
32/64-bit, 66/133-MHz bus interfaces
96 KB ultra-deep packet buffer with support for up to 16 MB
externally
Support for IEEE 802.3, 802.3u, 802.3z, and 802.3ab
standards
MII/GMII and TBI (SerDes style) transceiver interfaces
features include: TCP/UDP/IP
Advanced CPU offload segmentation, 9 KB jumbo frame
checksum offload, TCP
Dual high-speed CPUs
PC99 compliant: support for ACPI ver
MicrosoftPXE version 2.0, and statistics for SNMP 1.1a, Wake
on LAN,
MIB II,
®
Features wire speed operation at all speeds.
ideal for new high-speed network interface
The BCM5700 is LAN on Motherboard (LOM) applications,
cards (NIC) and
the
and PCI-X
enables
Support for both run PCI 2.2PCI-based orstandardsystems.
the BCM5700 to
in any
PCI-X
packet buffer allows the
The ultra-deep on-chipand receive at high speedsBCM5700 to
continuously transmit
in systems
while maintaining backward compatibility with today’s
networks.
On-chip CPUs perform advanced functions and allow the
BCM5700 to evolve with new standards. The CPUs also
features promote
Advanced offloadCPU utilization. high throughput, while
minimizing host
Combined with the BCM5401 and newer BroadcomACPI-
10/100/1000BASE-T PHYs, the BCM5700 supports
compliant Wake on LAN implementations.
provide advanced packet parsing capabilities, making the
BCM5700 an OSI L4 protocol aware device, providing many
advanced features and offloads.
where the PCI/PCI-X bus is shared with other devices.
Layer 2 priority encoding (802.3p) (up to 16 priority queues)
VLAN tagging (IEEE 802.3q)
Flow control (IEEE 802.3x)
Link aggregation (IEEE802.3ad)
Multiple power modes with programmable low power
operation
Low power design – 3.3 V/1.8 V, 0.18 µm CMOS
5V tolerant PCI I/Os
388-pin PBGA package
Ethernet-like MIB, and Ethernet MIB (802.3z, Clause 30)
manageability features enable NIC
Additionalcomply with relevant manageability and LOM for
designs to
standards
power operation—0.18 µm advanced
Provides lowcombined with programmable power process
technology,
management.
server and desktop applications.
BCM5700 10/100/1000 PCI-X NIC Reference Design

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