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AN666: DescriptionUSAGE GUIDE FOR SIM3U1XX, SIM3C1XX, AND SIM3L1XX DMA AND DTM MODULES; File Size238KB，34 Pages; ManufacturerSILABS; Websitehttp://www.silabs.com

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AN666 Overview

USAGE GUIDE FOR SIM3U1XX, SIM3C1XX, AND SIM3L1XX DMA AND DTM MODULES

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AN666

S A G E

UIDE FOR

M3U1

, S

M3C1

M3L1

DMA

A N D

DTM M

OD ULES

1. Introduction

The Direct Memory Access (DMA) (SiM3U1xx, SiM3C1xx, and SiM3L1xx) and Data Transfer Manager (DTM)

(SiM3L1xx) modules are complex data management modules intended to autonomously transfer data between

peripherals and memory. These modules can save system power consumption by allowing the core to enter a low

power state or process data in parallel to improve performance. This document discusses usage models for these

modules.

AND

SiM3xxxx

Address Space (RAM)

DMA Channel 1

USART0 TX

USART0 RX

DMA Channel 0

Figure 1. Transferring Data using the DMA and DTM modules

2. Key Points

This key topics of this document are:



Using

the DMA in a basic memory-to-memory data transfer



Using the DMA from a peripheral-to-memory data transfer



Using the DMA from memory to a peripheral data transfer



Complex multi-channel DMA transfers using the Data Transfer Manager (SiM3L1xx devices only)

3. Relevant Documentation

Precision32 Application Notes are listed on the following website: www.silabs.com/32bit-appnotes.



AN725:

Advanced Low Power Techniques for SiM3L1xx Devices



AN667: Getting Started with the Silicon Labs Precision32 IDE



AN670: Integrating Silicon Labs SiM3xxxx Devices into the Keil µVision IDE

Rev. 0.1 9/12

AN666

AN666

4. DMA Overview

The DMA consists of two modules: DMA controller (DMACTRL) and DMA peripheral crossbar (DMAXBAR). The

controller provides a single access point for all 16 (SiM3U1xx and SiM3C1xx) or 10 (SiM3L1xx) DMA channels and

the global DMA controls. The controller is also responsible for handling arbitration between channels. The DMA

peripheral crossbar assigns channels to a peripheral. When assigned and properly configured, the peripheral’s

data request signal will trigger a DMA channel to transfer data. Figure 2 shows a block diagram of the DMA

controller and DMA peripheral crossbar.

DMAXBARn

Module

Peripheral 0.0

DMACTRLn

Module

Channel Control

DMA Channel 0

(DMAn_CH0)

SiM3xxxx

RAM

Peripheral 0.1

Peripheral 0.2

Peripheral 0.3

Source Pointer

Destination Pointer

Configuration

Source Pointer

Destination Pointer

Configuration

Peripheral 0.x

Channel Status

DMA Channel 1

(DMAn_CH1)

Peripheral 1.0

Peripheral 1.1

Peripheral 1.2

Peripheral 1.3

Channel Software

Transfer Request

Global Controller

State and Enable

DMA Channel n

(DMAn_CHx)

Arbitration

Source Pointer

Destination Pointer

Configuration

Peripheral n.0

Peripheral n.1

Peripheral n.2

Peripheral n.3

Peripheral 1.y

Peripheral n.z

Figure 2. DMACTRL and DMACH Block Diagram

The channels have controls and flags in the DMACTRL registers. In addition, each channel has one or more

transfer descriptors stored in memory that describe the data transfer in detail. Each channel can have primary,

alternate, or scatter-gather descriptors. The BASEPTR and ABASEPTR registers in the controller point to the

starting address of these descriptors in memory. Firmware sets the BASEPTR field, and the controller hardware

automatically sets the ABASEPTR field based on the number of channels implemented in the module.

Each channel has separate enables, alternate enables, masks, software requests, programmable priority, and

status flags. The channels operate independently, but have a fixed arbitration order.

The STATE field reports the current status of the DMA controller, and the DMAENS bit indicates whether the global

DMA enable is set.

Rev. 0.1

AN666

4.1. DMA Channel Transfer Descriptors

Each channel has transfer descriptors stored in memory that describe the data transfer in detail. Each descriptor is

composed of four 32-bit words in memory organized as follows:

Source End Pointer (word 1):

The address of the last source data in the transfer.

Destination End Pointer (word 2):

The last destination address of the transfer.

Channel Configuration (word 3):

Configuration details for the transfer.

Alignment padding (word 4):

Not used by the DMA controller. Firmware may use this word for any

purpose.

Each channel can have primary, alternate, and scatter-gather descriptors. The primary and alternate descriptors

are organized in contiguous blocks in memory for each of the channels. The spacing for these descriptors is fixed,

so any unused channels must still be accounted for when placing descriptors in memory. The primary descriptors

must be placed at the start of an address block sized for both the primary and alternate descriptors. For SiM3U1xx,

SiM3C1xx, and SiM3L1xx devices that implement 16 or 10 DMA channels, the BASEPTR points to the start of the

primary descriptors and is 23 bits wide. The valid addresses for the BASEPTR field are multiples of 256

(0x0000_0100), and the required memory for all primary and alternate descriptors for 16 channels is 512 bytes.

The scatter-gather descriptors are more flexible and can appear anywhere in memory.

Channel 0’s primary descriptor begins at address offset 0x0000, Channel 1’s primary descriptor starts at offset

0x0010, and so on. The alternate descriptors begin at the next memory block (256 bytes), regardless of whether or

not the primary descriptors for the channels are in use.

Firmware originally sets the channel configuration descriptor; the DMA controller will modify this word as the

transfer progresses, so firmware should not write to this descriptor until any active transfers for the channel are

complete.

Figure 3 shows the fixed memory configuration for the descriptors.

Rev. 0.1

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