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AN725: DescriptionADVANCED LOW POWER TECHNIQUES FOR SiM3L1XX DEVICES; File Size503KB，28 Pages; ManufacturerSILABS; Websitehttp://www.silabs.com

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AN725 Overview

ADVANCED LOW POWER TECHNIQUES FOR SiM3L1XX DEVICES

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AN725

D VA N C E D

OWER

ECHNIQUES

EVICES

1. Introduction

The system power budget of a low power system has two components: active and low power mode. Active mode

periods include an active core executing code or a larger number of active peripherals. In low power mode periods,

the core enters a sleep state and fewer peripherals are active.

FOR

SiM3L1

Active Mode

Low Power

Mode

Figure 1. Defining the Power Budget—Active and Low Power Modes

SiM3L1xx devices have several features to address reducing power consumption in all operational modes to

achieve a longer product lifetime in battery-operated systems. This document addresses each of these features

and provides guidelines for achieving low power consumption in a variety of configurations and applications.

2. Key Points

This key topics of this document are as follows:



How

to reduce active mode time and power consumption



How to reduce low power mode power consumption



Measuring the low power modes on an SiM3L1xx MCU card



General power-saving tips

3. Relevant Documentation

Precision32™ Application Notes are listed on the following website: www.silabs.com/32bit-appnotes.



AN666:

Usage Guide for e SiM3U1xx,SiM3C1xx, and SiM3L1xx DMA and DTM Modules



AN720: Precision32™ Optimization Considerations for Code Size and Speed



AN667: Getting Started with the Silicon Labs Precision32 IDE



AN670: Getting Started with the Silicon Labs Precision32 AppBuilder

Rev. 0.1 9/12

AN725

AN725

4. Reducing Active Mode Power Consumption

In active mode, the core is fetching instructions from memory and executing those instructions, and a large number

of peripherals may be active at once. This section discusses ways to reduce the SiM3L1xx device power

consumption in active mode (Normal, PM1, PM4, or PM5).

4.1. Dynamic AHB/APB Clock Scaling

One of the easiest ways to reduce overall system power consumption is to reduce the active mode time, which

maximizes the amount of time spent in the low power mode.

If the longest path to the next low power mode is the execution of code (e.g., a math algorithm), then it is typically

beneficial to run the AHB clock at the fastest speed possible to reduce the time spent in active mode.

If the longest path to the next low power mode is the transfer or collection of data through a peripheral, it is best to

run the clock at the lowest speed required for the peripheral. For example, if using the UART at 115200 baud and

the core is waiting for data to finish transferring, then running the AHB and APB at the slowest clock to achieve

115200 baud may be the lowest power configuration. However, if data is being transferred memory to memory by

the DMA, running the clocks at the fastest speed possible yields the lowest power consumption.

Due to the clock system of the SiM3L1xx devices, the AHB and APB clocks can be dynamically changed quickly

and easily using the CLKCTRL module based on the needs of the application.

4.2. Using the DMA and DTM Modules

The Direct Memory Access (DMA) and Data Transfer Manager (DTM) modules help move data without core

intervention. This reduces overall power consumption by removing the power consumed during flash accesses.

Additionally, since the Cortex-M3 is a load-store architecture where data is loaded into and out of registers only,

multiple instructions are required to move data from one area of memory to another, so the DMA and DTM may be

faster than data moves by the core, depending on the AHB load.

Instead of performing the data moves, the core can either sleep using wait-for-interrupt (WFI) or wait-for-event

(WFE) instructions, or the core can perform other tasks in parallel, reducing the active mode time.

For more information on how to use the DMA and DTM modules, see “AN666:Usage Guide for e

SiM3U1xx,SiM3C1xx, and SiM3L1xx DMA and DTM Modules” on the Silicon Labs 32-bit application notes website:

www.silabs.com/32bit-appnotes.

4.3. Code Optimization

There are several different coding techniques, compiler, and library options available for the Precision32 devices.

These options will change both code size and execution speed, which may result in power consumption savings in

systems which aim to execute code in active mode as quickly as possible before entering a low power state. In

addition to getting to the low power mode more quickly, changing the project settings may lead to smaller code

footprints, compacting the code into a smaller area with fewer memory accesses. The power consumption benefits

of code optimization for speed or size will vary depending on the project requirements and code.

For more information on how to write efficient code and the various optimization settings, see”AN720:

Precision32™ Optimization Considerations for Code Size and Speed” on the Silicon Labs 32-bit application notes

website: www.silabs.com/32bit-appnotes.

Rev. 0.1

AN725

4.4. Code Dependency

In addition to dynamic clock management, the power consumption of the SiM3L1xx device will vary with the type of

code the core executes. For example, if the core executes a complex math routine with branches, the pipeline will

miss every time a branch is taken and new instructions must be fetched. This stall and fetch period causes more

flash accesses, which increases power consumption. In addition, the core executes a wide variety of instructions

and activates the memory bus to fetch data from RAM or flash for use in these routines. In contrast, a string of NOP

instructions will take less power because the core isn’t executing complex instructions.

The data shown in Figure 2 does not use adaptive voltage scaling or any other techniques to change power

consumption. All of these measurements were taken using the PLL as the clock source with a higher SPMD setting

(i.e., reduced flash access frequency) at AHB frequencies above 40 MHz. The APB clock is equal to the AHB

clock, when the APB is enabled.

As shown by the data, the flash access frequency (SPMD) has a direct effect on the code that includes branches,

since the core stalls when waiting for the new instructions, resulting in reduced power consumption. This means

that it may be more efficient to run at a faster frequency with the same current consumption to reduce overall time

spent in active mode. For the code that is a long string of NOPs, the core never has a pipeline miss and never

stalls, so there is no change in power consumption with a different flash speed mode.

For power sensitive applications, experimenting with various code styles and instruction mixes may result in

reduced power consumption in active mode.

Current

SPMD = 1

SPMD = 2

AHB and APB Clock (MHz)

NOP code, no APB clocks enabled, all LDOs at 1.8 V

NOP code, all APB clocks enabled, all LDOs at 1.8 V

complex code, no APB clocks enabled, all LDOs at 1.8 V

complex code, all APB clocks enabled, all LDOs at 1.8 V

Figure 2. Power Consumption Code Dependency

Rev. 0.1

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