Datasheet
R8C/35C Group
RENESAS MCU
R01DS0006EJ0100
Rev 1.00
Aug. 24, 2010
1.
1.1
Overview
Features
The R8C/35C Group of single-chip MCUs incorporates the R8C CPU core, employing sophisticated instructions
for a high level of efficiency. With 1 Mbyte of address space, and it is capable of executing instructions at high
speed. In addition, the CPU core boasts a multiplier for high-speed operation processing.
Power consumption is low, and the supported operating modes allow additional power control. These MCUs are
designed to maximize EMI/EMS performance.
Integration of many peripheral functions, including multifunction timer and serial interface, reduces the number of
system components.
The R8C/35C Group has data flash (1 KB × 4 blocks) with the background operation (BGO) function.
1.1.1
Applications
Electronic household appliances, office equipment, audio equipment, consumer equipment, etc.
R01DS0006EJ0100 Rev 1.00
Aug. 24, 2010
Page 1 of 54
R8C/35C Group
1. Overview
1.1.2
Specifications
Tables 1.1 and 1.2 outline the Specifications for R8C/35C Group.
Table 1.1
Item
CPU
Specifications for R8C/35C Group (1)
Function
Central processing
unit
Specification
R8C CPU core
• Number of fundamental instructions: 89
• Minimum instruction execution time:
50 ns (f(XIN) = 20 MHz, VCC = 2.7 to 5.5 V)
200 ns (f(XIN) = 5 MHz, VCC = 1.8 to 5.5 V)
• Multiplier: 16 bits × 16 bits
→
32 bits
• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits
→
32 bits
• Operation mode: Single-chip mode (address space: 1 Mbyte)
Refer to
Table 1.3 Product List for R8C/35C Group.
• Power-on reset
• Voltage detection 3 (detection level of voltage detection 0 and voltage
detection 1 selectable)
• Input-only: 1 pin
• CMOS I/O ports: 47, selectable pull-up resistor
• High current drive ports: 47
4 circuits: XIN clock oscillation circuit,
XCIN clock oscillation circuit (32 kHz),
High-speed on-chip oscillator (with frequency adjustment function),
Low-speed on-chip oscillator
• Oscillation stop detection: XIN clock oscillation stop detection function
• Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16
• Low power consumption modes:
Standard operating mode (high-speed clock, low-speed clock, high-speed
on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode
Real-time clock (timer RE)
• Number of interrupt vectors: 69
• External Interrupt: 9 (INT × 5, Key input × 4)
• Priority levels: 7 levels
• 14 bits × 1 (with prescaler)
• Reset start selectable
• Low-speed on-chip oscillator for watchdog timer selectable
• 1 channel
• Activation sources: 33
• Transfer modes: 2 (normal mode, repeat mode)
8 bits × 1 (with 8-bit prescaler)
Timer mode (period timer), pulse output mode (output level inverted every
period), event counter mode, pulse width measurement mode, pulse period
measurement mode
8 bits × 1 (with 8-bit prescaler)
Timer mode (period timer), programmable waveform generation mode (PWM
output), programmable one-shot generation mode, programmable wait one-
shot generation mode
16 bits × 1 (with 4 capture/compare registers)
Timer mode (input capture function, output compare function), PWM mode
(output 3 pins), PWM2 mode (PWM output pin)
16 bits × 2 (with 4 capture/compare registers)
Timer mode (input capture function, output compare function), PWM mode
(output 6 pins), reset synchronous PWM mode (output three-phase
waveforms (6 pins), sawtooth wave modulation), complementary PWM mode
(output three-phase waveforms (6 pins), triangular wave modulation), PWM3
mode (PWM output 2 pins with fixed period)
8 bits × 1
Real-time clock mode (count seconds, minutes, hours, days of week), output
compare mode
Memory
ROM, RAM, Data
flash
Power Supply Voltage detection
Voltage
circuit
Detection
I/O Ports
Programmable I/O
ports
Clock
Clock generation
circuits
Interrupts
Watchdog Timer
DTC (Data Transfer Controller)
Timer
Timer RA
Timer RB
Timer RC
Timer RD
Timer RE
R01DS0006EJ0100 Rev 1.00
Aug. 24, 2010
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R8C/35C Group
1. Overview
Table 1.2
Item
Serial
Interface
Specifications for R8C/35C Group (2)
Function
UART0, UART1
UART2
Specification
Clock synchronous serial I/O/UART × 2 channel
Clock synchronous serial I/O/UART, I
2
C mode (I
2
C-bus), multiprocessor
communication function
1 (shared with I
2
C-bus)
1 (shared with SSU)
Hardware LIN: 1 (timer RA, UART0)
10-bit resolution × 12 channels, includes sample and hold function, with sweep
mode
8-bit resolution × 2 circuits
2 circuits
• Programming and erasure voltage: VCC = 2.7 to 5.5 V
• Programming and erasure endurance: 10,000 times (data flash)
1,000 times (program ROM)
• Program security: ROM code protect, ID code check
• Debug functions: On-chip debug, on-board flash rewrite function
• Background operation (BGO) function
f(XIN) = 20 MHz (VCC = 2.7 to 5.5 V)
f(XIN) = 5 MHz (VCC = 1.8 to 5.5 V)
Typ. 6.5 mA (VCC = 5.0 V, f(XIN) = 20 MHz)
Typ. 3.5 mA (VCC = 3.0 V, f(XIN) = 10 MHz)
Typ. 3.5
µA
(VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz))
Typ. 2.0
µA
(VCC = 3.0 V, stop mode)
-20 to 85°C (N version)
-40 to 85°C (D version)
(1)
52-pin LQFP
Package code: PLQP0052JA-A (previous code: 52P6A-A)
Synchronous Serial
Communication Unit (SSU)
I
2
C bus
LIN Module
A/D Converter
D/A Converter
Comparator B
Flash Memory
Operating Frequency/Supply
Voltage
Current consumption
Operating Ambient Temperature
Package
Note:
1. Specify the D version if D version functions are to be used.
R01DS0006EJ0100 Rev 1.00
Aug. 24, 2010
Page 3 of 54
FPGA/CPLD
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