CAT93C86B
16-Kb Microwire Serial
EEPROM
Description
The CAT93C86B is a 16−Kb Serial EEPROM memory device
which is configured as either registers of 16 bits (ORG pin at V
CC
) or 8
bits (ORG pin at GND). Each register can be written (or read) serially
by using the DI (or DO) pin. The CAT93C86B features a self−timed
internal write with auto−clear. On−chip Power−On Reset circuit
protects the internal logic against powering up in the wrong state.
Features
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High Speed Operation: 4 MHz (5 V), 2 MHz (1.8 V)
1.8 V (1.65 V*) to 5.5 V Supply Voltage Range
Selectable x8 or x16 Memory Organization
Self−timed Write Cycle with Auto−clear
Sequential Read
Hardware and Software Write Protection
Power−up Inadvertent Write Protection
Low Power CMOS Technology
Program Enable (PE) Pin
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial and Extended Temperature Ranges
8−pin PDIP, SOIC, MSOP, TSSOP, 8−pad UDFN, and WLCSP
6−ball Packages
•
This Device is Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
†
V
CC
MSOP−8
Z SUFFIX
CASE 846AD
SOIC−8
X SUFFIX
CASE 751BE
UDFN−8
HU4 SUFFIX
CASE 517AZ
WLCSP−6
C6A SUFFIX
PRELIMINARY
PDIP−8
L SUFFIX
CASE 646AA
TSSOP−8
Y SUFFIX
CASE 948AL
SOIC−8
V SUFFIX
CASE 751BD
PIN CONFIGURATION
CS
SK
DI
DO
1
V
CC
PE
ORG
GND
Pin 1 1
A
VCC
B
C
SK
GND
2
CS
DI
DO
PDIP (L), SOIC (V, X),
TSSOP (Y),
UDFN (HU4), MSOP (Z)
WLCSP*, ** (C6A)
*ORG internally
connected to GND
**PE float
PIN FUNCTION
Pin Name
Function
Chip Select
Clock Input
Serial Data Input
Serial Data Output
Power Supply
Ground
Memory Organization
Program Enable
CS
SK
DI
DO
V
CC
ORG
CS
SK
PE
CAT93C86B
DI
DO
GND
GND
ORG
PE
Figure 1. Functional Symbol
*CAT93C86Bxx−xxL (T
A
=
−205C
to +855C)
†For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
Note:
When the ORG pin is connected to V
CC
, the
x16 organization is selected. When it is connected
to ground, the x8 pin is selected. If the ORG pin is
left unconnected, then an internal pull−up device will
select the x16 organization.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
©
Semiconductor Components Industries, LLC, 2013
September, 2013
−
Rev. 3
1
Publication Order Number:
CAT93C86B/D
CAT93C86B
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Storage Temperature
Voltage on Any Pin with Respect to Ground (Note 1)
Ratings
−65
to +150
−0.5
to +6.5
Units
°C
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The DC input voltage on any pin should not be lower than
−0.5
V or higher than V
CC
+ 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than
−1.5
V or overshoot to no more than V
CC
+ 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS
(Note 2)
Symbol
N
END
(Note 3)
T
DR
Endurance
Data Retention
Parameter
Min
1,000,000
100
Units
Program / Erase Cycles
Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Block Mode, V
CC
= 5 V, 25°C.
Table 3. D.C. OPERATING CHARACTERISTICS
Symbol
I
CC1
I
CC2
I
SB1
I
SB2
Parameter
Supply Current (Write)
Supply Current (Read)
Standby Current
(x8 Mode)
Standby Current
(x16 Mode)
Input Leakage Current
(V
CC
= +1.8 V to +5.5 V, T
A
=
−40°C
to +125°C, V
CC
= +1.65 V to +5.5 V, T
A
=
−20°C
to +85°C unless otherwise specified.)
Test Conditions
Write, V
CC
= 5.0 V
Read, DO open, f
SK
= 2 MHz, V
CC
= 5.0 V
V
IN
= GND or V
CC
CS = GND, ORG = GND
V
IN
= GND or V
CC
CS = GND,
ORG = Float or V
CC
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
CS = GND
4.5 V
≤
V
CC
< 5.5 V
4.5 V
≤
V
CC
< 5.5 V
1.65 V
≤
V
CC
< 4.5 V
1.65 V
≤
V
CC
< 4.5 V
4.5 V
≤
V
CC
< 5.5 V, I
OL
= 3 mA
4.5 V
≤
V
CC
< 5.5 V, I
OH
=
−400
mA
1.65 V
≤
V
CC
< 4.5 V, I
OL
= 1 mA
1.65 V
≤
V
CC
< 4.5 V, I
OH
=
−100
mA
V
CC
−
0.2
2.4
0.2
T
A
=
−40°C
to +85°C
T
A
=
−40°C
to +125°C
T
A
=
−40°C
to +85°C
T
A
=
−40°C
to +125°C
T
A
=
−40°C
to +85°C
T
A
=
−40°C
to +125°C
I
LO
V
IL1
V
IH1
V
IL2
V
IH2
V
OL1
V
OH1
V
OL2
V
OH2
Output Leakage
Current
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
T
A
=
−40°C
to +85°C
T
A
=
−40°C
to +125°C
−0.1
2
0
V
CC
x 0.7
Min
Max
2
500
2
5
1
3
1
2
1
2
0.8
V
CC
+ 1
V
CC
x 0.2
V
CC
+ 1
0.4
V
V
V
V
V
V
V
V
mA
mA
mA
Units
mA
mA
mA
I
LI
Table 4. PIN CAPACITANCE
(Note 4)
Symbol
C
OUT
C
IN
Test
Output Capacitance (DO)
Input Capacitance (CS, SK, DI, ORG)
Conditions
V
OUT
= 0 V
V
IN
= 0 V
Min
Typ
Max
5
5
Units
pF
pF
Table 5. POWER−UP TIMING
(Notes 4, 5)
Symbol
t
PUR
t
PUW
Parameter
Power−up to Read Operation
Power−up to Write Operation
Max
1
1
Units
ms
ms
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CAT93C86B
Device Operation
The CAT93C86B is a 16,384−bit nonvolatile memory
intended for use with industry standard microprocessors.
The CAT93C86B can be organized as either registers of 16
bits or 8 bits. When organized as X16, seven 13−bit
instructions control the reading, writing and erase
operations of the device. When organized as X8, seven
14−bit instructions control the reading, writing and erase
operations of the device. The CAT93C86B operates on a
single power supply and will generate on chip, the high
voltage required during any write operation.
Instructions, addresses, and write data are clocked into the
DI pin on the rising edge of the clock (SK). The DO pin is
normally in a high impedance state except when reading data
from the device, or when checking the ready/busy status
after a write operation.
The ready/busy status can be determined after the start of
a write operation by selecting the device (CS high) and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that the
device is ready for the next instruction. If necessary, the DO
pin may be placed back into a high impedance state during
chip select by shifting a dummy “1” into the DI pin. The DO
pin will enter the high impedance state on the falling edge of
the clock (SK). Placing the DO pin into the high impedance
state is recommended in applications where the DI pin and
the DO pin are to be tied together to form a common DI/O
pin.
The format for all instructions sent to the device is a
logical “1” start bit, a 2−bit (or 4−bit) opcode, 10−bit address
(an additional bit when organized X8) and for write
operations a 16−bit data field (8−bit for X8 organizations).
Note:
The Write, Erase, Write all and Erase all instructions
require PE = 1. If PE is left floating, 93C86B is in Program
Enabled mode. For Write Enable and Write Disable
instruction PE = don’t care.
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT93C86B will
come out of the high impedance state and, after sending an
initial dummy zero bit, will begin shifting out the data
addressed (MSB first). The output data bits will toggle on
the rising edge of the SK clock and are stable after the
specified time delay (t
PD0
or t
PD1
).
After the initial data word has been shifted out and CS
remains asserted with the SK clock continuing to toggle, the
device will automatically increment to the next address and
shift out the next data word in a sequential READ mode. As
long as CS is continuously asserted and SK continues to
toggle, the device will keep incrementing to the next address
automatically until it reaches to the end of the address space,
then loops back to address 0. In the sequential READ mode,
only the initial data word is preceeded by a dummy zero bit.
All subsequent data words will follow without a dummy
zero bit.
Write
After receiving a WRITE command, address and the data,
the CS (Chip Select) pin must be deselected for a minimum
of t
CSMIN
. The falling edge of CS will start the self clocking
clear and data store cycle of the memory location specified
in the instruction. The clocking of the SK pin is not
necessary after the device has entered the self clocking
mode. The ready/busy status of the CAT93C86B can be
determined by selecting the device and polling the DO pin.
Since this device features Auto−Clear before write, it is
NOT necessary to erase a memory location before it is
written into.
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