CCD linear image sensor
S12551-2048
Pixel size: 14 × 14
μm,
front-illuminated type,
high-speed response and high sensitivity
The S12551-2048 is a front-illuminated type CCD linear image sensor with high-speed line rate designed for applications such
as sorting machine.
Features
Pixel size: 14 × 14
μm
2048 pixels
High CCD node sensitivity: 13
μV/e
- typ.
Readout speed: 40 MHz max.
Anti-blooming function
Built-in electronic shutter
Applications
Foreign object screening
High-speed imaging
Structure
Parameter
Pixel size (H × V)
Number of pixels
Number of effective pixels
Image size (H × V)
Horizontal clock phase
Output circuit
Package
Window material
*1:
Resin sealing
Specification
14 × 14
μm
2068
2048
28.672 × 0.014 mm
Two-phase
Three-stage MOSFET source follower
24-pin ceramic DIP (refer to dimensional outline)
Quartz glass*
1
Absolute maximum ratings (Ta=25 °C, unless otherwise noted)
Parameter
Operating temperature
Storage temperature
Output transistor drain voltage
Reset drain voltage
Anti-blooming drain voltage
Horizontal input source voltage
Anti-blooming gate voltage
Horizontal input gate voltage
Summing gate voltage
Output gate voltage
Reset gate voltage
Transfer gate voltage
Horizontal shift register clock voltage
Symbol
Topr
Tstg
V
OD
V
RD
V
ABD
V
ISH
V
ABG
V
IGH
V
SG
V
OG
V
RG
V
TG
V
P1H
, V
P2H
Condition
Package temperature,
No condensation
No condensation
Value
-50 to +60
-50 to +70
-0.5 to +20
-0.5 to +18
-0.5 to +18
-0.5 to +18
-10 to +15
-10 to +15
-10 to +15
-10 to +15
-10 to +15
-10 to +15
-10 to +15
Unit
°C
°C
V
V
V
V
V
V
V
V
V
V
V
Note: During high-speed operation, the temperature of the sensor increases. Take heat dissipation measures as required to prevent
exceeding the absolute maximum ratings.
Exceeding the absolute maximum ratings even momentarily may cause a drop in product quality. Always be sure to the product
within the absolute maximum ratings.
www.hamamatsu.com
1
CCD linear image sensor
S12551-2048
Operating conditions (Ta=25 °C)
Parameter
Output transistor drain voltage
Reset drain voltage
Anti-blooming drain voltage
Horizontal input source voltage
Test point
Horizontal input gate voltage
High
Anti-blooming gate voltage
Low
High
Summing gate voltage
Low
Output gate voltage
Substrate voltage
High
Reset gate voltage
Low
High
Transfer gate voltage
Low
High
Horizontal shift register clock voltage
Low
External load resistance
Symbol
V
OD
V
RD
V
ABD
V
ISH
V
IGH
V
ABGH
V
ABGL
V
SGH
V
SGL
V
OG
V
SS
V
RGH
V
RGL
V
TGH
V
TGL
V
P1HH
, V
P2HH
V
P1HL
, V
P2HL
R
L
Min.
14
13
13
-
-5
2
-4
2
-5
3
-
8
-1
7
-5
2
-5
2.0
Typ.
15
14
14
V
RD
-4
5
-2
5
-4
5
0
9
0
8
-4
5
-4
2.2
Max.
16
15
15
-
-
8
0
8
-3
7
-
10
1
9
-3
8
-3
2.4
Unit
V
V
V
V
V
V
V
V
V
V
V
kΩ
Electrical characterisitics (Ta=25 °C, operating conditions: Typ., unless otherwise noted)
Parameter
Output signal frequency*
2
Without electronic shutter
Line rate
With electronic shutter
Horizontal shift register capacitance
Anti-blooming gate capacitance
Summing gate capacitance
Reset gate capacitance
Transfer gate capacitance
Charge transfer efficiency*
3
DC output level*
2
Output impedance*
2
Power consumption*
2
*
4
Symbol
fop
LRnes
LRes
C
P1H
, C
P2H
C
ABG
C
SG
C
RG
C
TG
CTE
Vo
Zo
P
Min.
-
-
-
-
-
-
-
-
0.99995
8
-
-
Typ.
20
9.5
9.5
220
80
10
10
120
0.99999
9
160
100
Max.
40
19.2
18.7
-
-
-
-
-
-
10
-
140
Unit
MHz
kHz
pF
pF
pF
pF
pF
-
V
Ω
mW
*2:
The value depends on the load resistance.
*3:
Charge transfer efficiency per pixel of CCD shift register, measured at half of the full well capacity
*4:
Power consumption of the on-chip amplifier plus load resistance
Electrical and optical characterisitics (Ta=25 °C, operating conditions: Typ., unless otherwise noted)
Parameter
Saturation output voltage
Full well capacity
CCD node sensitivity
Dark current (maximum of all effective pixels)
Readout noise*
6
Dynamic range*
7
Spectral response range
Photoresponse nonuniformity*
8
*
9
Image lag*
8
*5:
*6:
*7:
*8:
Symbol
Vsat
Csat
CCE
I
D
max
Nread
DR
λ
PRNU
Lag
Min.
-
70
11
-
-
1167
-
-
-
Typ.
Fw × Sv
100
13
15
40
2500
200 to 1000
±3
0.1
Max.
-
-
15
75
60
-
-
±10
1
Unit
V
ke
-
μV/e
-
e
-
/pixel/ms
e
-
rms
-
nm
%
%
Dark current is reduced to half for every 5 to 7 °C decrease in temperature.
Readout frequency 40 MHz
Dynamic range = Full well capacity / Readout noise
Measured at one-half of the saturation output (full well capacity) using LED light (peak emission wavelength: 470 nm)
Fixed pattern noise (peak to peak)
*9:
Photoresponse nonuniformity =
× 100 [%]
Signal
2
CCD linear image sensor
S12551-2048
Spectral response (without window, typical example)*
10
100
(Ta=25 °C)
100
(Ta=25 °C)
60
Photosensitivity [V/(μJ∙cm
2
)]
80
80
Quantum efficiency (%)
60
40
40
20
20
0
200 300 400 500 600 700 800 900 1000 1100
0
200 300 400 500 600 700 800 900 1000 1100
Wavelength (nm)
KMPDB0398EB
Wavelength (nm)
KMPDB0448EA
*10:
Spectral response with quartz glass is decreased according to
the spectral transmittance characteristics of window material.
Spectral transmittance characteristics of window material
100
(Typ. Ta=25 °C)
80
Transmittance (%)
60
40
20
0
200
300
400
500
600
700
800
900
1000
Wavelength (nm)
KMPDB0303EA
3
CCD linear image sensor
S12551-2048
Device structure (conceptual drawing of top view in dimensional outline)
23
22
21
20
19
18
17
16
Photodiode
D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 S1 S2 S3 S4
24
D1 D2 D3 D4
CCD horizontal shift register
S2045
S2046
S2047
S2048
D17 D18 D19 D20
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
Light-shielded section
KMPDC0483EA
4
CCD linear image sensor
S12551-2048
Timing chart
When not using electronic shutter
1 line output period (integration time)
ABG
Tpwv
TG
Tpwh, Tpws
P1H
P2H
SG
Tpwr
RG
OS
D1
D2
D19
D20
D3...D16, S1...S2048, D17, D18
Normal readout period
Dummy readout period*
1
2
3...2067
2068
Tovr
*
When making the integration time longer than the normal readout period, to carry away the dark current generated in the CCD
horizontal shift register, perform dummy readout after completion of the normal readout until right before rising transfer gate pulse.
KMPDC0484EB
TG
P1H, P2H*
11
SG
RG
TG - P1H
Parameter
Pulse width
Rise and fall times
Pulse width
Rise and fall times
Duty ratio
Pulse width
Rise and fall times
Duty ratio
Pulse width
Rise and fall times
Overlap time
Symbol
Tpwv
Tprv, Tpfv
Tpwh
Tprh, Tpfh
-
Tpws
Tprs, Tpfs
-
Tpwr
Tprr, Tpfr
Tovr
Min.
0.2
10
12.5
2
40
12.5
2
40
6
1
0.1
Typ.
0.4
-
25
-
50
25
-
50
12
-
0.2
Max.
-
-
-
-
60
-
-
60
-
-
-
Unit
μs
ns
ns
ns
%
ns
ns
%
ns
ns
μs
*11:
Symmetrical clock pulses should be overlapped at 50% of maximum pulse amplitude.
5
Wireless Connectivity
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