UNISONIC TECHNOLOGIES CO., LTD
UF840
8A, 500V, 0.85Ω, N-CHANNEL
POWER MOSFET
DESCRIPTION
Power MOSFET
The N-Channel enhancement mode silicon gate power
MOSFET is designed for high voltage, high speed power
switching applications such as switching regulators, switching
converters, solenoid, motor drivers, relay drivers.
FEATURES
* Low R
DS(ON)
< 0.85Ω @ V
GS
= 10V
* Single Pulse Avalanche Energy Rated
* Fast Switching Speeds
* Linear Transfer Characteristics
* High Input Impedance
SYMBOL
ORDERING INFORMATION
Package
TO-220
TO-220F1
TO-220F2
TO-220F
TO-220F3
TO-262
TO-263
TO-263
Pin Assignment
1
2
3
G
D
S
G
D
S
G
D
S
G
D
S
G
D
S
G
D
S
G
D
S
G
D
S
Packing
Tube
Tube
Tube
Tube
Tube
Tube
Tube
Tape Reel
Ordering Number
Lead Free
Halogen Free
UF840L-TA3-T
UF840G-TA3-T
UF840L-TF1-T
UF840G-TF1-T
UF840L-TF2-T
UF840G-TF2-T
UF840L-TF3-T
UF840G-TF3-T
UF840L-TF3T-T
UF840G-TF3T-T
UF840L-T2Q-T
UF840G-T2Q-T
UF840L-TQ2-T
UF840G-TQ2-T
UF840L-TQ2-R
UF840G-TQ2-R
Note: Pin Assignment: G: Gate
D: Drain
S: Source
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QW-R502-047.H
UF840
MARKING INFORMATION
PACKAGE
TO-220
TO-220F
TO-220F1
TO-220F2
TO-220F3
TO-262
TO-263
MARKING
Power MOSFET
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QW-R502-047.H
UF840
ABSOLUTE MAXIMUM RATINGS
(T
A
= 25°C, unless Otherwise Specified.)
Power MOSFET
PARAMETER
SYMBOL
RATINGS
UNIT
Drain to Source Voltage (T
J
=25°C ~125°C)
V
DSS
500
V
Drain to Gate Voltage (R
GS
= 20kΩ, T
J
=25°C ~125°C)
V
DGR
500
V
Gate to Source Voltage
V
GSS
±30
V
8.0
A
Continuous
I
D
Drain Current
Pulsed
I
DM
32
A
TO-220
134
TO-220F/TO-220F1
44
Power Dissipation (T
C
=25°C) TO-220F3
P
D
W
TO-220F2
46
TO-262/TO-263
134
Single Pulse Avalanche Energy
E
AS
510
mJ
Operating Temperature
T
OPR
-55 ~ +150
°C
Storage Temperature
T
STG
-55 ~ +150
°C
Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
THERMAL DATA
PARAMETER
SYMBOL
θ
JA
RATINGS
62.5
0.93
2.86
2.72
0.93
UNIT
°C/W
Junction to Ambient
TO-220
TO-220F/TO-220F1
TO-220F3
TO-220F2
TO-262/TO-263
Junction to Case
θ
JC
°C/W
ELECTRICAL SPECIFICATIONS
(T
A
=25°C, unless Otherwise Specified.)
SYMBOL
TEST CONDITIONS
BV
DSS
I
D
= 250μA, V
GS
= 0V
V
GS(TH)
V
GS
=V
DS
, I
D
= 250μA
I
D(ON)
V
DS
> I
D(ON)
x R
DS(ON)MAX
, V
GS
=10V
V
DS
=Rated BV
DSS
, V
GS
= 0V
I
DSS
V
DS
=0.8xRated BV
DSS
,V
GS
=0V,T
J
= 125°C
I
GSS
V
GS
= ±30V
MIN TYP MAX UNIT
500
V
2
4
V
8
A
25
μA
250 µA
±100 nA
0.73 0.85
60
260
60
90
116
13
22
750
130
16
70
300
70
110
120
Ω
ns
ns
ns
ns
nC
nC
nC
pF
pF
pF
PARAMETER
Drain-Source Breakdown Voltage
Gate Threshold Voltage
On-State Drain Current (Note 1)
Drain-Source Leakage Current
Gate-Source Leakage Current
Static Drain-Source On-State
R
DS(ON)
V
GS
=10V. I
D
= 4.4A
Resistance (Note 1)
Turn-On Delay Time
t
DLY(ON)
Turn-Off Delay Time
t
DLY(OFF)
V
DD
=30V, I
D
≈
1A, R
G
=9.1Ω, R
L
=30Ω
(Note 2)
Turn-On Rise Time
t
R
Turn-Off Fall Time
t
F
Total Gate Charge
Q
G(TOT)
V
GS
=10V, I
D
=8A,V
DS
=120V
Gate-Source Charge
Q
GS
I
G(REF)
=3.3mA (Note 3)
Gate-Drain Charge
Q
GD
Input Capacitance
C
ISS
Output Capacitance
C
OSS
V
DS
= 25V, V
GS
= 0V, f = 1.0MHz
Reverse Transfer Capacitance
C
RSS
Note : 1. Pulse Test: Pulse width≤300μs, Duty Cycle≤2%.
2. MOSFET Switching Times are Essentially Independent of Operating Temperature.
3. Gate Charge is Essentially Independent of Operating Temperature.
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QW-R502-047.H
UF840
INTERNAL PACKAGE INDUCTANCE
PARAMETER
SYMBOL
DRAIN INDUCTANCE
Measured from the contact screw on tab to center of die
L
D
Measured from the drain lead(6mm from package) to center of die
SOURCE INDUCTANCE
Measured from the source lead(6mm from header) to source bond pad
L
S
Remark:
Modified MOSFET symbol showing the internal devices inductances as below.
Power MOSFET
MIN TYP MAX UNIT
3.5
4.5
7.5
nH
nH
nH
SOURCE TO DRAIN DIODE SPECIFICATIONS
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNIT
Source to Drain Diode Voltage(Note 1)
V
SD
T
J
= 25°C, I
SD
= 8.0A, V
GS
= 0V
2
V
Continuous Source to Drain Current
I
SD
8
A
Note 2
Pulse Source to Drain Current
I
SDM
32
A
Reverse Recovery Time
t
rr
T
J
= 25°C, I
SD
= 8.0A, dI
SD
/dt = 100A/μs
210 475 970 ns
Reverse Recovery Charge
Q
RR
T
J
= 25°C, I
SD
= 8.0A, dI
SD
/dt = 100A/μs
2
4.6 8.2
μC
Notes: 1. Pulse Test: Pulse width≤300μs, Duty Cycle≤2%.
2. Modified MOSFET symbol showing the integral reverse P-N junction diode as below.
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QW-R502-047.H
UF840
TEST CIRCUITS AND WAVEFORMS
Power MOSFET
Unclamped Energy Test Circuit
Unclamped Energy Waveforms
Switching Time Test Circuit
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QW-R502-047.H
Embedded System
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