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APVV-32.000MHZ-N-R-V

Description
LVDS Output Clock Oscillator, 32MHz Nom, SMD, 6 PIN
CategoryPassive components    oscillator   
File Size4MB,7 Pages
ManufacturerAbracon
Websitehttp://www.abracon.com/index.htm
Environmental Compliance  
Download Datasheet Parametric View All

APVV-32.000MHZ-N-R-V Overview

LVDS Output Clock Oscillator, 32MHz Nom, SMD, 6 PIN

APVV-32.000MHZ-N-R-V Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
Reach Compliance Codecompliant
Other featuresTRI-STATE; STANDBY; ENABLE/DISABLE FUNCTION; COMPLEMENTARY OUTPUT; BULK
Maximum control voltage3.3 V
Minimum control voltage
maximum descent time0.001 ns
Frequency Adjustment - MechanicalNO
Frequency offset/pull rate100 ppm
frequency stability25%
linearity10%
Installation featuresSURFACE MOUNT
Nominal operating frequency32 MHz
Maximum operating temperature85 °C
Minimum operating temperature-30 °C
Oscillator typeLVDS
Output load100 OHM, 10 pF
physical size7.0mm x 5.08mm x 1.8mm
longest rise time0.001 ns
Maximum supply voltage3.63 V
Minimum supply voltage2.97 V
Nominal supply voltage3.3 V
surface mountYES
maximum symmetry55/45 %
3.3V CMOS/PECL/LVDS OUTPUT SMD VCXO
APVV SERIES
FEATURES:
Pb
RoHS/RoHS II Compliant and Pb free.
7.0 x 5.08 x 1.8mm
| | | | | | | | | | | | |
| |
• SONET, Fiber Channel, SERDES HDTV,
• CMOS, PECL
or LVDS Output
OBSAI, CPRI, PCI Express, 1394
• Low Integrated rms jitter (1ps max. over 12kHz to 20MHz
BW)
Low Profile, Seam-Sealed Package (5.08 x 7.0 x1.8mm)
Wide Frequency Pull Range (±100 ppm min.)
APPLICATIONS:
STANDARD SPECIFICATIONS:
Parameters
Frequency Range
Operating Temperature
Storage Temperature
Overall Frequency Stability
Supply Voltage (Vdd)
Control Voltage (Vc)
Linearity
Pullability
Transfer Function
Aging
CMOS
Tri-state Function
(Stand-by)
PECL (P option)
PECL (P1 option)
LVDS
CMOS
LVDS
PECL
Minimum
32.0
32.0
32.0
0
-55
-100
2.25
2.97
0.3
0
-10
±100
Typical
Maximum
200
640
640
+70
+125
+100
2.75
3.63
2.5
3.3
10
Units
MHz
°C
°C
ppm
V
V
%
ppm
ppm
Notes
Fund. or 3
rd
OT
Fund., 3
rd
OT, or Mult.
Fund., 3
rd
OT, or Mult.
See options
2.5
3.3
See options
See options
Standard
Vdd=2.5V±10%
Vdd=3.3V±10%
-3.0
+3.0
"1" (VIH≥0.7*Vdd) or Open: Oscillation
"0" (VIH<0.3*Vdd) :
Hi
Z
"1" (VIH≥0.7*Vdd) or Open:
Hi
Z
"0" (VIH<0.3*Vdd) :
Oscillation
"1" (VIH≥0.7*Vdd) or Open:
Oscillation
"0" (VIH<0.3*Vdd) :
Hi
Z
"1" (VIH≥0.7*Vdd) or Open: Oscillation
"0" (VIH<0.3*Vdd) :
Hi
Z
Minimum
Typical
35
45
55
60
2
2
1.5
1.2
50
4.0
3.0
2.0
2.0
0.5
0.5
0.5
0.5
3.0
3.0
3.0
3.0
Maximum
50
65
70
75
0.1*V
dd
3
2.5
2
1.5
55
7
5
4
4
1
1
1
1
7
7
7
7
Units
mA
V
Positive
@+25°C First year
Key Electrical Specifications – CMOS
Parameters
Supply Current (I
dd
)
Output Logic Level
Rise Time/Fall Time
Duty Cycle
Start-up Time
V
OH
V
OL
Tr/Tf
45
0.9*V
dd
Notes
32.000MHz ~ 63.999MHz
64.000MHz ~99.999MHz
100.000MHz ~ 149.999MHz
150.000MHz ~ 200.000MHz
32.000MHz ~ 63.999MHz
ns
%
64.000MHz ~99.999MHz
100.000MHz ~ 149.999MHz
150.000MHz ~ 200.000MHz
32.000MHz ~ 63.999MHz
64.000MHz ~99.999MHz
100.000MHz ~ 149.999MHz
150.000MHz ~ 200.000MHz
32.000MHz ~ 63.999MHz
Integrated Phase Jitter RMS (J
PH
)
ps
64.000MHz ~99.999MHz
100.000MHz ~ 149.999MHz
150.000MHz ~ 200.000MHz
32.000MHz ~ 63.999MHz
Period Jitter RMS (J
PER
)
ps
64.000MHz ~99.999MHz
100.000MHz ~ 149.999MHz
150.000MHz ~ 200.000MHz
ABRACON IS
ISO9001:2008
CE RTIFIED
Revised: 01.17.13
30332 E speranza, Rancho Santa Margarita, California 92688
tel 949-546-800
|
fax 949-546-80 1
| www.abracon.com
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0
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